Abstract: Provided is a semiconductor device including a substrate, a first vertical channel, a spacer, and a second vertical channel. The first vertical channel may have a sheet shape extending in a direction perpendicular to a surface of the substrate. The spacer may be provided at an end of the first vertical channel in an extension direction. The second vertical channel may be aligned with the first vertical channel on the spacer and have a sheet shape extending in a vertical direction.

Abstract: A semiconductor device includes a metal nitride layer, a channel provided in the metal nitride layer and including a two-dimensional (2D) semiconductor material, a source electrode provided on one side of the channel, a drain electrode provided on another side of the channel, a gate insulating layer provided in the channel, and a gate electrode provided on the gate insulating layer.

Abstract: A semiconductor device may include a substrate, a vertical channel, a gate electrode, and a conductive layer. The vertical channel may have a tube shape extending in a direction perpendicular to a surface of the substrate. The gate electrode may face the vertical channel with an outer insulating layer therebetween on an outer circumferential surface of the vertical channel. The conductive layer may face the vertical channel with an inner insulating layer therebetween on an inner circumferential surface of the vertical channel.

Abstract: A semiconductor device includes a dielectric wall provided in a direction perpendicular to a substrate, a first metal oxide field effect transistor (MOSFET) provided on one side surface of the dielectric wall, a second MOSFET provided above the first MOSFET in a direction perpendicular to the substrate, and a third MOSFET provided in parallel with the first MOSFET on the other side surface of the dielectric wall.

Abstract: Provided is a semiconductor device including a two-dimensional (2D) material. The semiconductor device may include a first channel including a first 2D material layer, a second channel apart from the first channel in a first direction and including a second 2D material layer, a common gate electrode between the first channel and the second channel, a first electrode and a second electrode apart from each other and respectively in contact with the first channel and the second channel, and a common electrode apart from the first electrode and the second electrode in a second direction intersecting the first direction and in contact with the first channel and the second channel. One of the first channel and the second channel may be an n-type channel and the other one may be a p-type channel.

Abstract: A semiconductor device includes a first channel layer and a second channel layer spaced from each other in a first direction and each include a two-dimensional (2D) semiconductor material, a first source electrode between the first channel layer and the second channel layer to be simultaneously in contact with the first channel layer and the second channel layer, a first drain electrode between the first channel layer and the second channel layer to be spaced apart from the first source electrode in a second direction perpendicular to the first direction and simultaneously in contact with the first channel layer and the second channel layer, a first gate electrode arranged in a first internal space surrounded by the first source electrode, the first drain electrode, the first channel layer, and the second channel layer, and a first gate insulating layer surrounding the first gate electrode in the first internal space.

Abstract: Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a source electrode provided on a substrate, a drain electrode disposed away from the source electrode, and a channel connected between the source electrode and the drain electrode, wherein the channel includes a plurality of first channel layers and plurality of second channel layers, and the gate electrode is provided on one surface and another surface of each of the plurality of the first channel layers and on one surface and another surface of each of the plurality of the second channel layers.

Abstract: Provided are a vertical-channel cell array transistor structure and a dynamic random-access memory (DRAM) device including the same. The vertical-channel cell array transistor structure includes a semiconductor substrate, a plurality of channels arranged in an array on the semiconductor substrate and each extending perpendicularly from the semiconductor substrate, a gate insulating layer on the plurality of channels, a plurality of word lines on the semiconductor substrate and extending in a first direction, and a two-dimensional (2D) material layer on at least one surface of each of the plurality of word lines.

Abstract: A semiconductor device is provided. The semiconductor device includes a metal layer, a semiconductor layer in electrical contact with the metal layer, a two-dimensional (2D) material layer disposed between the metal layer and the semiconductor layer and having a 2D crystal structure, and a metal compound layer disposed between the 2D material layer and the semiconductor layer.

Abstract: A method of pre-treating a substrate on which graphene will be directly formed may include pre-treating the substrate using a pre-treatment gas including at least a carbon source and hydrogen.

Abstract: A semiconductor device is provided. The semiconductor device includes a metal layer, a semiconductor layer in electrical contact with the metal layer, a two-dimensional (2D) material layer disposed between the metal layer and the semiconductor layer and having a 2D crystal structure, and a metal compound layer disposed between the 2D material layer and the semiconductor layer.

Abstract: A stacked structure may include a first material layer, a two-dimensional material layer on the first material layer, and a second material layer on the two-dimensional material layer. The two-dimensional material layer may include a plurality of holes that each expose a portion of the first material layer. The second material layer may be coupled to the first material layer through the plurality of holes.

Abstract: Provided is a method of forming an interconnect structure. The method includes preparing a substrate including a first metal layer and a first insulating layer, selectively forming a carbon layer having an sp2 bonding structure on the first metal layer, selectively forming a second insulating layer on the first insulating layer, forming a third insulating layer to cover the second insulating layer, and forming a second metal layer electrically connected to the first metal layer.

Abstract: Provided are a semiconductor device including a two-dimensional material and a method of manufacturing the semiconductor device. The semiconductor device may include a substrate, first and second two-dimensional material layers on the substrate and junctioned to each other in a lateral direction to form a coherent interface, a first source electrode and a first drain electrode on the first two-dimensional material layer, a first gate electrode between the first source electrode and the first drain electrode, a second source electrode and a second drain electrode on the second two-dimensional material layer, and a second gate electrode between the second source electrode and the second drain electrode.

Abstract: A transistor structure may include a semiconductor structure may include a substrate; a source electrode and a drain electrode spaced apart from each other on the substrate; a channel layer connected to the source electrode and the drain electrode; a gate insulating layer on the channel layer; and a gate electrode on the gate insulating layer. The channel layer may include a two-dimensional semiconductor material. The source electrode and the drain electrode each may include a graphene layer and a metal layer. The graphene layer may be formed by as-growing on the substrate. The graphene layer and the metal layer may be side by side in a vertical direction with respect to a surface of the substrate.

Abstract: Provided is a method of forming an interconnect structure. The method includes preparing a substrate including a first metal layer and a first insulating layer, selectively forming a carbon layer having an sp2 bonding structure on the first metal layer, selectively forming a second insulating layer on the first insulating layer, forming a third insulating layer to cover the second insulating layer, and forming a second metal layer electrically connected to the first metal layer.

Abstract: A semiconductor memory device and a device including the same are provided. The semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate; bit line structures extending across the word lines in a second direction crossing the first direction; contact pad structures between the word lines and between the bit line structures; and spacers between the bit line structures and the contact pad structures. The spacers include a boron nitride layer.

Abstract: Disclosed is a semiconductor device including a surface-treated semiconductor layer. The semiconductor device includes a metal layer, a semiconductor layer electrically contacting the metal layer and having a surface treated with an element having an electron affinity of about 4 eV or greater, and a two-dimensional (2D) material layer disposed between the metal layer and the semiconductor layer and having a 2D crystal structure.

Abstract: Provided are a semiconductor device including a two-dimensional (2D) material and an electronic device including the semiconductor device. The semiconductor device may include a channel layer including a two-dimensional (2D) semiconductor material, a channel portion, and an extension portion on both sides of the channel portion, a source electrode and a drain electrode respectively on both sides of the channel layer, a gate electrode surrounding the channel portion, a first insulating layer between the channel portion of the channel layer and the gate electrode, and a second insulating layer on the extension portion of the channel layer. The second insulating layer may include a different material than a material of the first insulating layer. The second insulating layer may include a n-type dopant or p-type dopant. A dopant in the extension portion may be the same as a dopant in the second insulating layer.

Abstract: Disclosed are a semiconductor device, a method of manufacturing the same, and an electronic element and an electronic apparatus each including the semiconductor device. The semiconductor device may include a substrate, a channel layer on the substrate, a first electrode and a second electrode on two opposite ends of the channel layer, respectively, and spaced apart from each other, a gate electrode on the channel layer and spaced apart from the first electrode and the second electrode, a gate dielectric material provided between the channel layer and the gate electrode, and a chalcogen compound layer being at least one of between the gate dielectric material and the channel layer, between the first electrode and the channel layer, and between the second electrode and the channel layer.