Patents by Inventor Kyung-Hwa Kang
Kyung-Hwa Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961775Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.Type: GrantFiled: November 8, 2022Date of Patent: April 16, 2024Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Gyu Wan Han, Won Bae Bang, Ju Hyung Lee, Min Hwa Chang, Dong Joo Park, Jin Young Khim, Jae Yun Kim, Se Hwan Hong, Seung Jae Yu, Shaun Bowers, Gi Tae Lim, Byoung Woo Cho, Myung Jea Choi, Seul Bee Lee, Sang Goo Kang, Kyung Rok Park
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Patent number: 11919122Abstract: A substrate processing apparatus includes: a conveyor belt configured to have an outer surface on which a bottom surface of a substrate is seated; and a polishing head unit configured to face an upper surface of the substrate, wherein the polishing head unit includes: a polishing head connected to a driver; a polishing pad configured to face the polishing head; a polishing pad fixing ring disposed between the polishing head and the polishing pad; and a temperature sensor configured to overlap the polishing pad fixing ring and to be spaced apart from the polishing pad fixing ring.Type: GrantFiled: September 29, 2020Date of Patent: March 5, 2024Assignees: SAMSUNG DISPLAY CO., LTD., KCTECH CO., LTD.Inventors: Seung Bae Kang, Sung Hyeon Park, Jung Gun Nam, Joon-Hwa Bae, Kyung Bo Lee, Keun Woo Lee, Woo Jin Cho, Byoung Kwon Choo
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Patent number: 10223011Abstract: A storage device includes a nonvolatile memory device and a controller configured to generate a read command according to a request of an external host device and transmit the read command to the nonvolatile memory device. The nonvolatile memory device is configured to perform a read operation in response to the read command, to output read data to the controller, and to store information of the read operation in an internal register.Type: GrantFiled: February 21, 2017Date of Patent: March 5, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Hyejin Yim, Jinyub Lee, Kyung-Hwa Kang, Minseok Kim, Minsu Kim, Sung-Won Yun
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Publication number: 20170300252Abstract: A storage device includes a nonvolatile memory device and a controller configured to generate a read command according to a request of an external host device and transmit the read command to the nonvolatile memory device. The nonvolatile memory device is configured to perform a read operation in response to the read command, to output read data to the controller, and to store information of the read operation in an internal register.Type: ApplicationFiled: February 21, 2017Publication date: October 19, 2017Inventors: HYEJIN YIM, JINYUB LEE, KYUNG-HWA KANG, MINSEOK KIM, MINSU KIM, SUNG-WON YUN
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Patent number: 9666283Abstract: Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.Type: GrantFiled: May 12, 2016Date of Patent: May 30, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Kyung-Hwa Kang, Sang-Wan Nam, Donghyuk Chae, ChiWeon Yoon
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Patent number: 9478290Abstract: A memory device is provided as follows. A memory cell array includes strings including first and second strings. Each string includes a ground selection transistor and cell transistors. First and second ground selection lines are connected to a gate of a first ground selection transistor of the first string and a gate of a second ground selection transistor of the second string, respectively. First and second cell gate lines are connected to a gate of a first cell transistor of the first string and a gate of a second cell transistor of the second string, respectively. A first interconnection unit electrically connects a first portion of the first cell gate line to a first portion of the second cell gate line. A second interconnection unit electrically connects a second portion of the first cell gate line to a second portion of the second cell gate line.Type: GrantFiled: November 11, 2015Date of Patent: October 25, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Wan Nam, Kyung-Hwa Kang, Dae-Seok Byeon, Chi-Weon Yoon
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Publication number: 20160254054Abstract: Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.Type: ApplicationFiled: May 12, 2016Publication date: September 1, 2016Inventors: Kyung-Hwa KANG, Sang-Wan NAM, Donghyuk CHAE, ChiWeon YOON
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Patent number: 9349455Abstract: Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.Type: GrantFiled: October 20, 2015Date of Patent: May 24, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Kyung-Hwa Kang, Sang-Wan Nam, Donghyuk Chae, ChiWeon Yoon
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Publication number: 20160042792Abstract: Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.Type: ApplicationFiled: October 20, 2015Publication date: February 11, 2016Inventors: Kyung-Hwa Kang, Sang-Wan Nam, Donghyuk Chae, ChiWeon Yoon
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Patent number: 9240239Abstract: Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.Type: GrantFiled: January 30, 2015Date of Patent: January 19, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Kyung-Hwa Kang, Sang-Wan Nam, Donghyuk Chae, ChiWeon Yoon
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Publication number: 20150138890Abstract: Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.Type: ApplicationFiled: January 30, 2015Publication date: May 21, 2015Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyung-Hwa KANG, Sang-Wan NAM, Donghyuk CHAE, ChiWeon YOON
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Patent number: 8976591Abstract: According to example embodiments, a nonvolatile memory device includes a first and a second NAND string. The first NAND string includes a first string selection transistor, a first local ground and a first global ground selection transistor, and first memory cells stacked in a direction perpendicular to a substrate. The second NAND string includes a second string selection transistor, a second local ground and a second global ground selection transistor, and second memory cells stacked in the direction perpendicular to the substrate. The device includes a selection line driver including path transistors configured to select and provide at least one operation voltage to the first and second string selection transistors, the first and second local and global ground selection transistors. The first and second string selection transistors are electrically isolated from each other, and the first and second global ground selection transistors are electrically connected.Type: GrantFiled: September 14, 2012Date of Patent: March 10, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Wan Nam, Kyung-Hwa Kang, Junghoon Park
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Patent number: 8971114Abstract: Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.Type: GrantFiled: February 8, 2012Date of Patent: March 3, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Kyung-Hwa Kang, Sang-Wan Nam, Donghyuk Chae, ChiWeon Yoon
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Patent number: 8625367Abstract: Memory devices and program methods thereof, the memory devices including a memory cell array with a three-dimensional structure, a voltage generator configured to supply a pass voltage and a program voltage to the memory cell array, and a control logic configured to make the rising slope of the pass voltage variable with a program loop during a program operation. The memory device may improve a program speed by adjusting the rising slope of the pass voltage according to the program loop.Type: GrantFiled: May 21, 2012Date of Patent: January 7, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Won Yun, ChiWeon Yoon, Kyung-Hwa Kang, JinTae Kim
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Patent number: 8570808Abstract: A nonvolatile memory device includes a 3D memory cell array having words lines that extend from a lowest memory cell array layer closest to a substrate to a highest memory cell array layer farthest from the substrate, a voltage generator circuit generating first and second voltage signals, and a row selecting circuit that simultaneously applies the first voltage signal to a selected word line and the second voltage signal to an unselected word line. The selected word line and the unselected word line have different resistances, yet the first voltage signal is applied to the selected word line and the second voltage signal is applied to the unselected word line with a same rising slope over a defined period of time.Type: GrantFiled: July 20, 2011Date of Patent: October 29, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-hoon Park, Kyung-Hwa Kang, Chi-Weon Yoon, Sang-Wan Nam, Sung-Won Yun
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Publication number: 20130170297Abstract: According to example embodiments, a nonvolatile memory device includes a first and a second NAND string. The first NAND string includes a first string selection transistor, a first local ground and a first global ground selection transistor, and first memory cells stacked in a direction perpendicular to a substrate. The second NAND string includes a second string selection transistor, a second local ground and a second global ground selection transistor, and second memory cells stacked in the direction perpendicular to the substrate. The device includes a selection line driver including path transistors configured to select and provide at least one operation voltage to the first and second string selection transistors, the first and second local and global ground selection transistors. The first and second string selection transistors are electrically isolated from each other, and the first and second global ground selection transistors are electrically connected.Type: ApplicationFiled: September 14, 2012Publication date: July 4, 2013Inventors: Sang-Wan NAM, Kyung-Hwa KANG, Junghoon PARK
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Publication number: 20120300561Abstract: Memory devices and program methods thereof, the memory devices including a memory cell array with a three-dimensional structure, a voltage generator configured to supply a pass voltage and a program voltage to the memory cell array, and a control logic configured to make the rising slope of the pass voltage variable with a program loop during a program operation. The memory device may improve a program speed by adjusting the rising slope of the pass voltage according to the program loop.Type: ApplicationFiled: May 21, 2012Publication date: November 29, 2012Inventors: Sung-Won YUN, ChiWeon YOON, Kyung-Hwa KANG, JinTae KIM
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Publication number: 20120201080Abstract: Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.Type: ApplicationFiled: February 8, 2012Publication date: August 9, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyung-Hwa KANG, Sang-Wan NAM, Donghyuk CHAE, ChiWeon YOON
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Publication number: 20120033501Abstract: Disclosed is a nonvolatile memory device which includes a 3D memory cell array having words lines that extend from a lowest memory cell array layer closest to a substrate to a highest memory cell array layer farthest from the substrate, a voltage generator circuit generating first and second voltage signals, and a row selecting circuit that simultaneously applies the first voltage signal to a selected word line and the second voltage signal to an unselected word line. The selected word line and the unselected word line have different resistances, yet the first voltage signal is applied to the selected word line and the second voltage signal is applied to the unselected word line with a same rising slope over a defined period of time.Type: ApplicationFiled: July 20, 2011Publication date: February 9, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-hoon Park, Kyung-Hwa Kang, Chi-Weon Yoon, Sang-Wan Nam, Sung-Won Yun
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Patent number: 6632772Abstract: A method of coating a catalyst to a support for use in acrolein oxidation reaction. Metallic salt components of the catalyst including molybdate, vanadate and tungstate are dissolved in a liquid to form a suspension of particles of the catalyst. The precipitation of the catalyst particles is controlled by homogenizing the catalyst particles suspended in the liquid. The phase separation between the catalyst particles and the liquid can be substantially slowed down by the homogenization. Then the catalyst is coated on an inert support by applying the suspension of the catalyst particles to the support. In the suspension, the total weight of water is about 0.8 to about 5 times of the total weight of the metallic salts in the catalyst. This method of preparing suspension minimizes the amount of the liquid required to dissolve the metallic salts, which reduces the amount of time and energy to be used in evaporating the liquid from the suspension.Type: GrantFiled: December 22, 2000Date of Patent: October 14, 2003Assignee: LG Chemical, Ltd.Inventors: Won-Ho Lee, Kyung-Hwa Kang, Dong-Hyun Ko, Young-Chang Byun