Patents by Inventor Kyung-In Choi

Kyung-In Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12230630
    Abstract: A semiconductor device includes a semiconductor substrate having first and second regions therein, a first lower semiconductor pattern, which protrudes from the semiconductor substrate in the first region and extends in a first direction across the semiconductor substrate, and a first gate electrode, which extends across the first lower semiconductor pattern and the semiconductor substrate in a second direction. A plurality of semiconductor sheet patterns are provided, which are spaced apart from each other in a third direction to thereby define a vertical stack of semiconductor sheet patterns, on the first lower semiconductor pattern. A first gate insulating film is provided, which separates the plurality of semiconductor sheet patterns from the first gate electrode. A second lower semiconductor pattern is provided, which protrudes from the semiconductor substrate in the second region. A plurality of wire patterns are provided, which are spaced apart from each other on the second lower semiconductor pattern.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: February 18, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung In Choi, Do Young Choi, Dong Myoung Kim, Jin Bum Kim, Hae Jun Yu
  • Publication number: 20240372002
    Abstract: A semiconductor device includes; an active pattern on a substrate, gate structures in which each gate structure includes a gate electrode intersecting the active pattern and a gate capping pattern on the gate electrode, a source/drain pattern disposed on the active pattern between adjacent gate structures, a lower active contact connected to the source/drain pattern, an etching stop film extending along an upper surface of the lower active contact without contacting an upper surface of the gate capping pattern, and an upper active contact connected to the lower active contact, wherein a bottom surface of the upper active contact is lower than the upper surface of the gate capping pattern.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Inventors: Kyung In Choi, Hae Jun Yu, Sung Hun Jung
  • Patent number: 12080796
    Abstract: A semiconductor device includes; an active pattern on a substrate, gate structures in which each gate structure includes a gate electrode intersecting the active pattern and a gate capping pattern on the gate electrode, a source/drain pattern disposed on the active pattern between adjacent gate structures, a lower active contact connected to the source/drain pattern, an etching stop film extending along an upper surface of the lower active contact without contacting an upper surface of the gate capping pattern, and an upper active contact connected to the lower active contact, wherein a bottom surface of the upper active contact is lower than the upper surface of the gate capping pattern.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: September 3, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung In Choi, Hae Jun Yu, Sung Hun Jung
  • Publication number: 20240105773
    Abstract: There is provided a semiconductor device having improved performance and reliability. A semiconductor device comprises an active pattern extending in a first direction, a gate structure including a gate electrode, a gate spacer, and a gate capping pattern on the active pattern, the gate electrode extending in a second direction different from the first direction and the gate capping pattern including a lower gate capping pattern and an upper gate capping pattern; a source/drain pattern disposed on the active pattern; and a source/drain etch stop film disposed on an upper surface of the source/drain pattern and extending along a sidewall of the gate spacer. The lower gate capping pattern is disposed on an upper surface of the gate electrode and an upper surface of the gate spacer, and the source/drain etch stop film does not extend along a sidewall of the lower gate capping pattern.
    Type: Application
    Filed: June 12, 2023
    Publication date: March 28, 2024
    Inventors: Hae Jun YU, Kyung In CHOI, Soon Wook JUNG
  • Patent number: 11735663
    Abstract: Example semiconductor devices and methods for fabricating a semiconductor device are disclosed. An example device may include a substrate, a first semiconductor pattern spaced apart from the substrate, a first antioxidant pattern extending along a bottom surface of the first semiconductor pattern and spaced apart from the substrate, and a field insulating film on the substrate. The insulating film may cover at least a part of a side wall of the first semiconductor pattern. The first antioxidant pattern may include a first semiconductor material film doped with a first impurity.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: August 22, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Bum Kim, Gyeom Kim, Da Hye Kim, Jae Mun Kim, Il Gyou Shin, Seung Hun Lee, Kyung In Choi
  • Publication number: 20230108041
    Abstract: A semiconductor device includes an active pattern which includes a lower pattern extending in a first direction, and sheet patterns spaced apart from the lower pattern in a second direction perpendicular to an upper surface of the lower pattern, each sheet pattern including an upper surface and a lower surface, a gate structure disposed on the lower pattern and including a gate electrode and a gate insulating film, the gate electrode and the gate insulating film surrounding each sheet pattern, and a source/drain pattern disposed on at least one side of the gate structure. The gate structure includes inter-gate structures that are disposed between the lower pattern and a lowermost sheet pattern and between two sheet patterns, and contacts the source/drain pattern. The gate insulating film includes a horizontal portion with a first thickness, and a first vertical portion with a second thickness different from the first thickness.
    Type: Application
    Filed: July 14, 2022
    Publication date: April 6, 2023
    Inventors: Hae Jun YU, Dong Suk SHIN, Soon Wook JUNG, Kyung In CHOI
  • Publication number: 20230040132
    Abstract: A method of manufacturing a semiconductor device includes: forming first to third preliminary active patterns on a substrate to have different intervals therebetween, forming first and second field insulating layers between the first and second preliminary active patterns and between the second and third preliminary active patterns, respectively, and forming first to third gate electrodes respectively on first to third active patterns formed based on the first to third preliminary active patterns, separated by first and second gate isolation structures.
    Type: Application
    Filed: May 11, 2022
    Publication date: February 9, 2023
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun Mo PARK, Kyu Bong CHOI, Yeon Ho PARK, Eun Sil PARK, Jin Seok LEE, Wang Seop LIM, Kyung In CHOI
  • Publication number: 20220399330
    Abstract: A semiconductor device includes a semiconductor substrate having first and second regions therein, a first lower semiconductor pattern, which protrudes from the semiconductor substrate in the first region and extends in a first direction across the semiconductor substrate, and a first gate electrode, which extends across the first lower semiconductor pattern and the semiconductor substrate in a second direction. A plurality of semiconductor sheet patterns are provided, which are spaced apart from each other in a third direction to thereby define a vertical stack of semiconductor sheet patterns, on the first lower semiconductor pattern. A first gate insulating film is provided, which separates the plurality of semiconductor sheet patterns from the first gate electrode. A second lower semiconductor pattern is provided, which protrudes from the semiconductor substrate in the second region. A plurality of wire patterns are provided, which are spaced apart from each other on the second lower semiconductor pattern.
    Type: Application
    Filed: January 10, 2022
    Publication date: December 15, 2022
    Inventors: Kyung In Choi, Do Young Choi, Dong Myoung Kim, Jin Bum Kim, Hae Jun Yu
  • Publication number: 20220302310
    Abstract: A semiconductor device includes; an active pattern on a substrate, gate structures in which each gate structure includes a gate electrode intersecting the active pattern and a gate capping pattern on the gate electrode, a source/drain pattern disposed on the active pattern between adjacent gate structures, a lower active contact connected to the source/drain pattern, an etching stop film extending along an upper surface of the lower active contact without contacting an upper surface of the gate capping pattern, and an upper active contact connected to the lower active contact, wherein a bottom surface of the upper active contact is lower than the upper surface of the gate capping pattern.
    Type: Application
    Filed: August 31, 2021
    Publication date: September 22, 2022
    Inventors: KYUNG IN CHOI, HAE JUN YU, SUNG HUN JUNG
  • Publication number: 20220123145
    Abstract: Example semiconductor devices and methods for fabricating a semiconductor device are disclosed. An example device may include a substrate, a first semiconductor pattern spaced apart from the substrate, a first antioxidant pattern extending along a bottom surface of the first semiconductor pattern and spaced apart from the substrate, and a field insulating film on the substrate. The insulating film may cover at least a part of a side wall of the first semiconductor pattern. The first antioxidant pattern may include a first semiconductor material film doped with a first impurity.
    Type: Application
    Filed: December 30, 2021
    Publication date: April 21, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jin Bum KIM, Gyeom KIM, Da Hye KIM, Jae Mun KIM, Il Gyou SHIN, Seung Hun LEE, Kyung In CHOI
  • Patent number: 11233150
    Abstract: Example semiconductor devices and methods for fabricating a semiconductor device are disclosed. An example device may include a substrate, a first semiconductor pattern spaced apart from the substrate, a first antioxidant pattern extending along a bottom surface of the first semiconductor pattern and spaced apart from the substrate, and a field insulating film on the substrate. The insulating film may cover at least a part of a side wall of the first semiconductor pattern. The first antioxidant pattern may include a first semiconductor material film doped with a first impurity.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: January 25, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Bum Kim, Gyeom Kim, Da Hye Kim, Jae Mun Kim, Il Gyou Shin, Seung Hun Lee, Kyung In Choi
  • Publication number: 20210098626
    Abstract: Example semiconductor devices and methods for fabricating a semiconductor device are disclosed. An example device may include a substrate, a first semiconductor pattern spaced apart from the substrate, a first antioxidant pattern extending along a bottom surface of the first semiconductor pattern and spaced apart from the substrate, and a field insulating film on the substrate. The insulating film may cover at least a part of a side wall of the first semiconductor pattern. The first antioxidant pattern may include a first semiconductor material film doped with a first impurity.
    Type: Application
    Filed: June 24, 2020
    Publication date: April 1, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jin Bum KIM, Gyeom KIM, Da Hye KIM, Jae Mun KIM, Il Gyou SHIN, Seung Hun LEE, Kyung In CHOI
  • Patent number: 10593557
    Abstract: A method of manufacturing a semiconductor device, the method including forming dummy gate structures on a substrate; forming spacers on sidewalls of the dummy gate structures; forming a preliminary first interlayer insulation pattern to fill a gap between adjacent spacers; etching an upper portion of the preliminary first interlayer insulation pattern through a first etching process to form a preliminary second interlayer insulation pattern; implanting an ion on the dummy gate structures, the spacers, and the preliminary second interlayer insulation pattern through an ion-implanting process; etching an upper portion of the preliminary second interlayer insulation pattern through a second etching process to form an interlayer insulation pattern having a flat upper surface; and forming a capping pattern on the interlayer insulation pattern to fill a gap between the spacers.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: March 17, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-In Choi, Sang-Hoon Han, Sun-Jung Kim, Tae-Gon Kim, Hyun-Chul Song
  • Patent number: 10449475
    Abstract: Provided is a method for manufacturing an expandable artificial media for water treatment by recycling waste liquid crystal display (LCD) glass and waste bottle glass generated from waste electric and electronic products. Therefore, the objective of the present invention is to activate the efficiency of resource circulation and energy utilization, which are green technology, and to minimize the discharge of greenhouse gases and pollutants by artificially manufacturing media for water treatment, as a filtering technique for water pollution, wherein in the artificial media manufactured by a series of automation processes, waste LCD glass and waste bottle glass are recycled through foaming.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: October 22, 2019
    Inventors: Seong Pil Choi, Kyung In Choi
  • Publication number: 20190164776
    Abstract: A method of manufacturing a semiconductor device, the method including forming dummy gate structures on a substrate; forming spacers on sidewalls of the dummy gate structures; forming a preliminary first interlayer insulation pattern to fill a gap between adjacent spacers; etching an upper portion of the preliminary first interlayer insulation pattern through a first etching process to form a preliminary second interlayer insulation pattern; implanting an ion on the dummy gate structures, the spacers, and the preliminary second interlayer insulation pattern through an ion-implanting process; etching an upper portion of the preliminary second interlayer insulation pattern through a second etching process to form an interlayer insulation pattern having a flat upper surface; and forming a capping pattern on the interlayer insulation pattern to fill a gap between the spacers.
    Type: Application
    Filed: September 6, 2018
    Publication date: May 30, 2019
    Inventors: Kyung-In CHOI, Sang-Hoon HAN, Sun-Jung KIM, Tae-Gon KIM, Hyun-Chul SONG
  • Publication number: 20190051554
    Abstract: A wafer support assembly can include a wafer chuck including a first surface and a second surface, where the first surface can have a central region that is configured to hold a wafer during ion implantation into the wafer, and an edge region surrounding the central region beyond an edge of the wafer when held in the central region, and the second surface opposing the first surface. An edge mask structure can cover at least a portion of the edge region of the first surface, where the edge mask structure can have a mask body with an inclined side surface facing the central region.
    Type: Application
    Filed: December 7, 2017
    Publication date: February 14, 2019
    Inventors: Hyun Chul Song, Tae Gon Kim, Kyung In Choi, Sun Hong Choi, HanMei Choi, Sang Hoon Han
  • Patent number: 10164017
    Abstract: A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: December 25, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yuichiro Sasaki, Bong Soo Kim, Tae Gon Kim, Yoshiya Moriyama, Seung Hyun Song, Alexander Schmidt, Abraham Yoo, Heung Soon Lee, Kyung In Choi
  • Publication number: 20180353886
    Abstract: Provided is a method for manufacturing an expandable artificial media for water treatment by recycling waste liquid crystal display (LCD) glass and waste bottle glass generated from waste electric and electronic products. Therefore, the objective of the present invention is to activate the efficiency of resource circulation and energy utilization, which are green technology, and to minimize the discharge of greenhouse gases and pollutants by artificially manufacturing media for water treatment, as a filtering technique for water pollution, wherein in the artificial media manufactured by a series of automation processes, waste LCD glass and waste bottle glass are recycled through foaming.
    Type: Application
    Filed: March 25, 2016
    Publication date: December 13, 2018
    Inventors: Seong Pil CHOI, Kyung In CHOI
  • Patent number: 10141427
    Abstract: A semiconductor device includes a gate pattern on a substrate, a multi-channel active pattern under the gate pattern to cross the gate pattern and having a first region not overlapping the gate pattern and a second region overlapping the gate pattern, a diffusion layer in the multi-channel active pattern along the outer periphery of the first region and including an impurity having a concentration, and a liner on the multi-channel active pattern, the liner extending on lateral surfaces of the first region and not extending on a top surface of the first region. Related fabrication methods are also described.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: November 27, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-In Choi, Gyeom Kim, Hong-Sik Yoon, Bon-Young Koo, Wook-Je Kim
  • Publication number: 20180158911
    Abstract: A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.
    Type: Application
    Filed: February 2, 2018
    Publication date: June 7, 2018
    Inventors: Yuichiro SASAKI, Bong Soo KIM, Tae Gon KIM, Yoshiya MORIYAMA, Seung Hyun SONG, Alexander SCHMIDT, Abraham YOO, Heung Soon LEE, Kyung In CHOI