Abstract: A discrete cosine transform circuit for processing an 8.times.8 block and two 4.times.8 blocks, comprising a first shuffle circuit for performing a first one-dimensional discrete cosine transform, a second shuffle circuit for performing a second one-dimensional discrete cosine transform, a first multiplexing circuit for selecting inputs to input terminals of adders/subtracters in the second shuffle circuit according to an input block size, ROMs for storing a data table therein to support all cosine matrices to perform a matrix multiplication operation based on the input block size, and a second multiplexing circuit for selecting a desired one of outputs from the ROMs according to the input block size. Therefore, according to the present invention, common and different parts for the process of two different block sizes are all implemented on a single circuit and controlled to process forward and inverse discrete cosine transforms.