Abstract: A method of controlling a towing mode of an eco-friendly vehicle, may easily charge a battery of a towed vehicle by selecting one of a charge mode during traveling, a regenerative braking charge mode, and a coasting charge mode for charging the battery of the towed vehicle when a towing vehicle tows the towed vehicle so that a motor of the towed vehicle is driven by a negative charge torque for charging the battery when the towing vehicle accelerates or decelerates, and furthermore, may easily perform the assist of the traveling driving force of the towing vehicle by selecting a discharge mode during traveling in a state in which the towed vehicle does not need to be charged to the amount of charge of the battery of the towed vehicle greater than or equal to a reference value so that the motor of the towed vehicle is driven by a positive driving torque by discharging the battery of the towed vehicle.

Abstract: A hydrogen supply method includes a two-side heat exchange mode in which both introducing a second fluid into a hydrogen storage part after the second fluid exchanges heat with a first fluid in a second heat exchanger in a state in which a compressor is driven to compress the first fluid and introducing the second fluid into the hydrogen storage part after the second fluid is heated or cooled in a thermal device are performed. The method also includes a one-side heat exchange mode in which one of introducing the second fluid into the hydrogen storage part after the second fluid exchanges heat with the first fluid in the second heat exchanger in a state in which the compressor is driven to compress the first fluid and introducing the second fluid into the hydrogen storage part after the second fluid is heated or cooled in the thermal device is performed.

Abstract: An apparatus of verifying a software integrity of a vehicle controller and a method thereof includes a communication device that provides a communication interface with a software management system, and a controller which is configured to obtain first verification data of the vehicle controller from the software management system, obtains second verification data from the vehicle controller, and verifies an integrity of software loaded in the vehicle controller based on the obtained first verification data and the obtained second verification data.

Abstract: The present invention provides an immunogenic composition comprising a Streptococcus pneumoniae polysaccharide-protein conjugate, comprising a capsular polysaccharide derived from one or more selected from the group consisting of serotypes 1, 2, 3, 4, 5, 6A, 6B, 7F, 8, 9N, 9V, 10A, 11A, 12F, 14, 15B, 17F, 18C, 19A, 19F, 20, 22F, 23F, and 33F, derived from Streptococcus pneumoniae; and one or 2 or more of carrier proteins conjugated to the respective capsular polysaccharide, and method of preparation thereof. Through one example of the present invention, an immunogenic composition for preventing or treating pneumococcal infection can be provided.

Abstract: A method for decoding an image based on an intra prediction, comprising: obtaining a first prediction pixel of a first region in a current block by using a neighboring pixel adjacent to the current block; obtaining a second prediction pixel of a second region in the current block by using the first prediction pixel of the first region; and decoding the current block based on the first and the second prediction pixels.

Abstract: Disclosed are novel compounds of Chemical Formula 1, optical isomers of the compounds, and pharmaceutically acceptable salts of the compounds or the optical isomers. The compounds, isomers, and salts exhibit excellent activity as GLP-1 receptor agonists. In particular, they, as GLP-1 receptor agonists, exhibit excellent glucose tolerance, thus having a great potential to be used as therapeutic agents for metabolic diseases. Moreover, they exhibit excellent pharmacological safety for cardiovascular systems.

Abstract: An embodiment of the present disclosure is a virtual home service apparatus including, a communicator, a home information collector for obtaining a design drawing of the home, and obtaining a 3D drawing by converting the design drawing, a home appliance identifier for obtaining an internal image and SLAM information of the home, and identifying the location and state of the home appliance based on the internal image and the SLAM information, and a virtual home implementator for generating virtual home information by reflecting the location and state of the home appliance to the 3D drawing. One or more among an autonomous driving vehicle, a user terminal, and a server according to an embodiment of the present disclosure may be associated with or converged with an Artificial Intelligence module, an Unmanned Aerial Vehicle (UAV), a robot, an Augmented Reality (AR) apparatus, a Virtual Reality (VR), 5G service-related apparatus, etc.

Abstract: An embodiment of the present disclosure is a vehicle information-linked content providing apparatus which provides content linked with information provided by a vehicle, the apparatus comprising a storage configured to store a plurality of event data and a plurality of background data, a transceiver configured to receive vehicle information including character matching information, and a controller configured to: select event data including a character designated by the character matching information; select background data including an event designated by the event data; and transmit, through the transceiver, content data including the selected event data and the selected background data.

Abstract: A vertical memory device includes a substrate having a cell array region and a connection region positioned on an exterior of the cell array region. Gate electrode layers are stacked on the cell array region and the connection region of the substrate, forming a stepped structure in the connection region. Channel structures are disposed in the cell array region, extending in a direction perpendicular to an upper surface of the substrate, while passing through the gate electrode layers. Dummy channel structures are disposed in the connection region, extending in the same direction as the channel structures, while passing through the gate electrode layers forming the stepped structure. First semiconductor patterns are disposed below the channel structures, and second semiconductor patterns are disposed below the dummy channel structures. The first and second semiconductor patterns include polycrystalline semiconductor materials.

Abstract: An embodiment of the present disclosure is a virtual home service apparatus including, a communicator, a home information collector for obtaining a design drawing of the home, and obtaining a 3D drawing by converting the design drawing, a home appliance identifier for obtaining an internal image and SLAM information of the home, and identifying the location and state of the home appliance based on the internal image and the SLAM information, and a virtual home implementator for generating virtual home information by reflecting the location and state of the home appliance to the 3D drawing. One or more among an autonomous driving vehicle, a user terminal, and a server according to an embodiment of the present disclosure may be associated with or converged with an Artificial Intelligence module, an Unmanned Aerial Vehicle (UAV), a robot, an Augmented Reality (AR) apparatus, a Virtual Reality (VR), 5G service-related apparatus, etc.

Abstract: A vertical memory device is provided as follows. A substrate has a cell array region and a connection region adjacent to the cell array region. A first gate stack includes gate electrode layers spaced apart from each other in a first direction perpendicular to the substrate. The gate electrode layers extends from the cell array region to the connection region in a second direction perpendicular to the first direction to form a first stepped structure on the connection region. The first stepped structure includes a first gate electrode layer and a second gate electrode layer sequentially stacked. The second gate electrode layer includes a first region having the same length as a length of the first gate electrode layer and a second region having a shorter length than the length of the first gate electrode layer.

Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers alternately stacked on a substrate, a channel layer penetrating through the gate electrodes and the interlayer insulating layers, and a gate dielectric layer disposed on an external surface of the channel layer between the gate electrodes and the channel layer. In addition, the channel layer includes a first region extended in a direction perpendicular to a top surface of the substrate and a second region connected to the first region in a lower portion of the first region and including a plane inclined with respect to the top surface of the substrate.

Abstract: A vertical memory device is provided as follows. A substrate has a cell array region and a connection region adjacent to the cell array region. A first gate stack includes gate electrode layers spaced apart from each other in a first direction perpendicular to the substrate. The gate electrode layers extends from the cell array region to the connection region in a second direction perpendicular to the first direction to form a first stepped structure on the connection region. The first stepped structure includes a first gate electrode layer and a second gate electrode layer sequentially stacked. The second gate electrode layer includes a first region having the same length as a length of the first gate electrode layer and a second region having a shorter length than the length of the first gate electrode layer.

Abstract: A vertical memory device includes a substrate having a cell array region and a connection region positioned on an exterior of the cell array region. Gate electrode layers are stacked on the cell array region and the connection region of the substrate, forming a stepped structure in the connection region. Channel structures are disposed in the cell array region, extending in a direction perpendicular to an upper surface of the substrate, while passing through the gate electrode layers. Dummy channel structures are disposed in the connection region, extending in the same direction as the channel structures, while passing through the gate electrode layers forming the stepped structure. First semiconductor patterns are disposed below the channel structures, and second semiconductor patterns are disposed below the dummy channel structures. The first and second semiconductor patterns include polycrystalline semiconductor materials.

Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers alternately stacked on a substrate, a channel layer penetrating through the gate electrodes and the interlayer insulating layers, and a gate dielectric layer disposed on an external surface of the channel layer between the gate electrodes and the channel layer. In addition, the channel layer includes a first region extended in a direction perpendicular to a top surface of the substrate and a second region connected to the first region in a lower portion of the first region and including a plane inclined with respect to the top surface of the substrate.

Abstract: A three-dimensional (3D) semiconductor device includes a plurality of gate electrodes stacked on a substrate in a direction normal to a top surface of the substrate, a channel structure passing through the gate electrodes and connected to the substrate, and a void disposed in the substrate and positioned below the channel structure.

Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers alternately stacked on a substrate, a channel layer penetrating through the gate electrodes and the interlayer insulating layers, and a gate dielectric layer disposed on an external surface of the channel layer between the gate electrodes and the channel layer. In addition, the channel layer includes a first region extended in a direction perpendicular to a top surface of the substrate and a second region connected to the first region in a lower portion of the first region and including a plane inclined with respect to the top surface of the substrate.

Abstract: A vertical memory device is provided as follows. A substrate has a cell array region and a connection region adjacent to the cell array region. A first gate stack includes gate electrode layers spaced apart from each other in a first direction perpendicular to the substrate. The gate electrode layers extends from the cell array region to the connection region in a second direction perpendicular to the first direction to form a first stepped structure on the connection region. The first stepped structure includes a first gate electrode layer and a second gate electrode layer sequentially stacked. The second gate electrode layer includes a first region having the same length as a length of the first gate electrode layer and a second region having a shorter length than the length of the first gate electrode layer.

Abstract: A three-dimensional (3D) semiconductor device includes a plurality of gate electrodes stacked on a substrate in a direction normal to a top surface of the substrate, a channel structure passing through the gate electrodes and connected to the substrate, and a void disposed in the substrate and positioned below the channel structure.

Abstract: A NAND-type flash memory device and method for programming the NAND-type flash memory device are provided. The method may include applying a voltage of 0 V to an unselected string select line, applying the voltage of 0 V to a selected bit line, applying a supply voltage to a selected string select line, and applying a dummy pass voltage to a dummy word line, the dummy pass voltage being in a range between 0 V to a pass voltage. The method may further include applying the supply voltage to an unselected bit line, applying the pass voltage to a selected word line, applying the pass voltage to an unselected word line; and applying a program voltage to the selected word line.