Abstract: The present disclosure relates to an organic electroluminescent compound, a plurality of host materials, and an organic electroluminescent device comprising the same. By comprising the organic electroluminescent compound according to the present disclosure or by comprising a specific combination of compounds according to the present disclosure as a plurality of host materials, it is possible to produce an organic electroluminescent device having improved luminous efficiency, and/or lifetime properties compared to the conventional organic electroluminescent devices.

Abstract: A driving performance verification device and driving performance verification method of an autonomous vehicle is proposed. The device includes a reception unit for operating in a driving mode and receiving sensing data sensed and provided in real time while driving is conducted on an actual road, a branch unit for operating in the driving mode, and branching and providing the sensing data into first sensing data and second sensing data, a sensing data regeneration unit for storing in real time the second sensing data and regenerating the stored second sensing data in a verification mode, and a verification control unit for providing the first sensing data to an ECU in the driving mode, obtaining first driving data, providing the second sensing data to the ECU in the verification mode, obtaining second driving data, and verifying driving performance by comparing the first driving data with the second driving data.

Abstract: Disclosed is a console operation device including a base plate, at least one solenoid disposed in the base plate, a guide rail disposed in front of the base plate, and a manipulator mounted on the guide rail to move on the guide rail, wherein the at least one solenoid includes a first magnet having a polarity, wherein the manipulator includes a second magnet having a polarity, wherein the manipulator is configured to be moved based on the polarities of the first and second magnets.

Abstract: An embodiment of the present disclosure is a virtual home service apparatus including, a communicator, a home information collector for obtaining a design drawing of the home, and obtaining a 3D drawing by converting the design drawing, a home appliance identifier for obtaining an internal image and SLAM information of the home, and identifying the location and state of the home appliance based on the internal image and the SLAM information, and a virtual home implementator for generating virtual home information by reflecting the location and state of the home appliance to the 3D drawing. One or more among an autonomous driving vehicle, a user terminal, and a server according to an embodiment of the present disclosure may be associated with or converged with an Artificial Intelligence module, an Unmanned Aerial Vehicle (UAV), a robot, an Augmented Reality (AR) apparatus, a Virtual Reality (VR), 5G service-related apparatus, etc.

Abstract: An embodiment of the present disclosure is a vehicle information-linked content providing apparatus which provides content linked with information provided by a vehicle, the apparatus comprising a storage configured to store a plurality of event data and a plurality of background data, a transceiver configured to receive vehicle information including character matching information, and a controller configured to: select event data including a character designated by the character matching information; select background data including an event designated by the event data; and transmit, through the transceiver, content data including the selected event data and the selected background data.

Abstract: A vertical memory device includes a substrate having a cell array region and a connection region positioned on an exterior of the cell array region. Gate electrode layers are stacked on the cell array region and the connection region of the substrate, forming a stepped structure in the connection region. Channel structures are disposed in the cell array region, extending in a direction perpendicular to an upper surface of the substrate, while passing through the gate electrode layers. Dummy channel structures are disposed in the connection region, extending in the same direction as the channel structures, while passing through the gate electrode layers forming the stepped structure. First semiconductor patterns are disposed below the channel structures, and second semiconductor patterns are disposed below the dummy channel structures. The first and second semiconductor patterns include polycrystalline semiconductor materials.

Abstract: An embodiment of the present disclosure is a virtual home service apparatus including, a communicator, a home information collector for obtaining a design drawing of the home, and obtaining a 3D drawing by converting the design drawing, a home appliance identifier for obtaining an internal image and SLAM information of the home, and identifying the location and state of the home appliance based on the internal image and the SLAM information, and a virtual home implementator for generating virtual home information by reflecting the location and state of the home appliance to the 3D drawing. One or more among an autonomous driving vehicle, a user terminal, and a server according to an embodiment of the present disclosure may be associated with or converged with an Artificial Intelligence module, an Unmanned Aerial Vehicle (UAV), a robot, an Augmented Reality (AR) apparatus, a Virtual Reality (VR), 5G service-related apparatus, etc.

Abstract: A vertical memory device is provided as follows. A substrate has a cell array region and a connection region adjacent to the cell array region. A first gate stack includes gate electrode layers spaced apart from each other in a first direction perpendicular to the substrate. The gate electrode layers extends from the cell array region to the connection region in a second direction perpendicular to the first direction to form a first stepped structure on the connection region. The first stepped structure includes a first gate electrode layer and a second gate electrode layer sequentially stacked. The second gate electrode layer includes a first region having the same length as a length of the first gate electrode layer and a second region having a shorter length than the length of the first gate electrode layer.

Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers alternately stacked on a substrate, a channel layer penetrating through the gate electrodes and the interlayer insulating layers, and a gate dielectric layer disposed on an external surface of the channel layer between the gate electrodes and the channel layer. In addition, the channel layer includes a first region extended in a direction perpendicular to a top surface of the substrate and a second region connected to the first region in a lower portion of the first region and including a plane inclined with respect to the top surface of the substrate.

Abstract: A vertical memory device is provided as follows. A substrate has a cell array region and a connection region adjacent to the cell array region. A first gate stack includes gate electrode layers spaced apart from each other in a first direction perpendicular to the substrate. The gate electrode layers extends from the cell array region to the connection region in a second direction perpendicular to the first direction to form a first stepped structure on the connection region. The first stepped structure includes a first gate electrode layer and a second gate electrode layer sequentially stacked. The second gate electrode layer includes a first region having the same length as a length of the first gate electrode layer and a second region having a shorter length than the length of the first gate electrode layer.

Abstract: A vertical memory device includes a substrate having a cell array region and a connection region positioned on an exterior of the cell array region. Gate electrode layers are stacked on the cell array region and the connection region of the substrate, forming a stepped structure in the connection region. Channel structures are disposed in the cell array region, extending in a direction perpendicular to an upper surface of the substrate, while passing through the gate electrode layers. Dummy channel structures are disposed in the connection region, extending in the same direction as the channel structures, while passing through the gate electrode layers forming the stepped structure. First semiconductor patterns are disposed below the channel structures, and second semiconductor patterns are disposed below the dummy channel structures. The first and second semiconductor patterns include polycrystalline semiconductor materials.

Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers alternately stacked on a substrate, a channel layer penetrating through the gate electrodes and the interlayer insulating layers, and a gate dielectric layer disposed on an external surface of the channel layer between the gate electrodes and the channel layer. In addition, the channel layer includes a first region extended in a direction perpendicular to a top surface of the substrate and a second region connected to the first region in a lower portion of the first region and including a plane inclined with respect to the top surface of the substrate.

Abstract: A three-dimensional (3D) semiconductor device includes a plurality of gate electrodes stacked on a substrate in a direction normal to a top surface of the substrate, a channel structure passing through the gate electrodes and connected to the substrate, and a void disposed in the substrate and positioned below the channel structure.

Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers alternately stacked on a substrate, a channel layer penetrating through the gate electrodes and the interlayer insulating layers, and a gate dielectric layer disposed on an external surface of the channel layer between the gate electrodes and the channel layer. In addition, the channel layer includes a first region extended in a direction perpendicular to a top surface of the substrate and a second region connected to the first region in a lower portion of the first region and including a plane inclined with respect to the top surface of the substrate.

Abstract: A vertical memory device is provided as follows. A substrate has a cell array region and a connection region adjacent to the cell array region. A first gate stack includes gate electrode layers spaced apart from each other in a first direction perpendicular to the substrate. The gate electrode layers extends from the cell array region to the connection region in a second direction perpendicular to the first direction to form a first stepped structure on the connection region. The first stepped structure includes a first gate electrode layer and a second gate electrode layer sequentially stacked. The second gate electrode layer includes a first region having the same length as a length of the first gate electrode layer and a second region having a shorter length than the length of the first gate electrode layer.

Abstract: A three-dimensional (3D) semiconductor device includes a plurality of gate electrodes stacked on a substrate in a direction normal to a top surface of the substrate, a channel structure passing through the gate electrodes and connected to the substrate, and a void disposed in the substrate and positioned below the channel structure.

Abstract: A NAND-type flash memory device and method for programming the NAND-type flash memory device are provided. The method may include applying a voltage of 0 V to an unselected string select line, applying the voltage of 0 V to a selected bit line, applying a supply voltage to a selected string select line, and applying a dummy pass voltage to a dummy word line, the dummy pass voltage being in a range between 0 V to a pass voltage. The method may further include applying the supply voltage to an unselected bit line, applying the pass voltage to a selected word line, applying the pass voltage to an unselected word line; and applying a program voltage to the selected word line.

Abstract: In a non-volatile memory system, a plurality of main memory cells for storing data is arranged in a data cell array and a plurality of reference memory cells is arranged in a reference cell array. The reference cell array includes first reference word lines connected to first reference memory cells and extending, second reference word lines connected to second reference memory cells and extending alternately with the first reference word lines, reference bit lines to which the first and the second reference memory cells are alternately connected in a line and a combined cell having a pair of the first and second reference memory cells and generating a reference signal for processing the data. The first and the second reference memory cells have different cell characteristics. The stability of the reference signal is improved irrespective of the differentiation of the first and the second reference memory cells.

Abstract: In a method of storing data in a nonvolatile memory device, a program operation is performed on target memory cells among a plurality of memory cells based on a program voltage. A verification operation is performed on the target memory cells based on a verification voltage to determine whether all of the target memory cells are completely programmed. The verification voltage is changed depending on the program operation.

Abstract: In a non-volatile memory system, a plurality of main memory cells for storing data is arranged in a data cell array and a plurality of reference memory cells is arranged in a reference cell array. The reference cell array includes first reference word lines connected to first reference memory cells and extending, second reference word lines connected to second reference memory cells and extending alternately with the first reference word lines, reference bit lines to which the first and the second reference memory cells are alternately connected in a line and a combined cell having a pair of the first and second reference memory cells and generating a reference signal for processing the data. The first and the second reference memory cells have different cell characteristics. The stability of the reference signal is improved irrespective of the differentiation of the first and the second reference memory cells.