Abstract: An image processing apparatus includes a memory configured to store compressed data; and frame buffer compressing circuitry which includes encoder circuitry configured to compress at least some of source data to generate the compressed data and transmit the compressed data to the memory, and decoder circuitry configured to read and decompress the compressed data from the memory, in which the compressed data includes a payload and a header including actual compressed data and flag, the frame buffer compressing circuitry is configured to reflect a result obtained by comparing an accumulated compressibility corresponding to the compressed data with a reference compressibility in the flag, and is configured to perform compression or decompression in a lossy mode or a lossless mode depending on the flag.

Abstract: An image processing apparatus includes a memory configured to store compressed data; and frame buffer compressing circuitry which includes encoder circuitry configured to compress at least some of source data to generate the compressed data and transmit the compressed data to the memory, and decoder circuitry configured to read and decompress the compressed data from the memory, in which the compressed data includes a payload and a header including actual compressed data and flag, the frame buffer compressing circuitry is configured to reflect a result obtained by comparing an accumulated compressibility corresponding to the compressed data with a reference compressibility in the flag, and is configured to perform compression or decompression in a lossy mode or a lossless mode depending on the flag.

Abstract: Provided is an image processing device configured to compress first image data. The image processing device includes an encoding circuit configured to compress the first image data into second image data including prediction data and residual data, compress the second image data into third image data by performing entropy encoding on the second image data, generate a header representing a compression ratio of the third image data, and store the third image data along with the header in a memory device as compressed first image data.

Abstract: Provided is an image processing device configured to compress first image data. The image processing device includes an encoding circuit configured to compress the first image data into second image data including prediction data and residual data, compress the second image data into third image data by performing entropy encoding on the second image data, generate a header representing a compression ratio of the third image data, and store the third image data along with the header in a memory device as compressed first image data.

Abstract: A video decoder may perform, based on an operation mode, at least one of a first decoding operation to restore a first bin value based on a first context value, a second decoding operation to restore a second bin value based on an updated first context value or a second context value, a third decoding operation to restore a third bin value based on the updated first context value or a third context value, and a fourth decoding operation to restore at least one bypass bin value without a context value. Based on the operation mode, the video decoder may output the first bin value, the at least one bypass bin value, the first bin value and the at least one bypass bin value, the first bin value and one of the second and third bin values, or at least one of the first, second, and third bin values.

Abstract: Provided is an image processing device configured to compress first image data. The image processing device includes an encoding circuit configured to compress the first image data into second image data including prediction data and residual data, compress the second image data into third image data by performing entropy encoding on the second image data, generate a header representing a compression ratio of the third image data, and store the third image data along with the header in a memory device as compressed first image data.

Abstract: An application processor (AP) includes intellectual property (IP) blocks and a system bus having a first command controller and a second command controller. Each of the first command controller and the second command controller includes a command distributor, a command buffer, and a command arbiter. Each command distributor receives first through third commands from a central processing unit (CPU). Each command buffer sequentially receives a first command and a second command from the command distributor and outputs the first command and the second command at different time slots. Each command arbiter receives the first and second commands from the command buffer and a third command from the command distributor and selectively outputs the same. First data corresponding the first command, second data corresponding to the second command, and a run-marker are stored in the command buffer.

Abstract: A video decoder may perform, based on an operation mode, at least one of a first decoding operation to restore a first bin value based on a first context value, a second decoding operation to restore a second bin value based on an updated first context value or a second context value, a third decoding operation to restore a third bin value based on the updated first context value or a third context value, and a fourth decoding operation to restore at least one bypass bin value without a context value. Based on the operation mode, the video decoder may output the first bin value, the at least one bypass bin value, the first bin value and the at least one bypass bin value, the first bin value and one of the second and third bin values, or at least one of the first, second, and third bin values.

Abstract: A bit stream processing device may include a virtual division memory, a stream shift buffer, a decoder circuit, and a controller. The virtual division memory may be divided into a plurality of group memory regions configured to store a plurality of stream groups in the respective group memory regions and to output a memory bit stream. The stream groups may be included in an input bit stream. The stream shift buffer is configured to receive and store the memory bit stream and output a buffer bit stream. The decoder circuit is configured to perform a decoding operation on the buffer bit stream from the stream shift buffer. The controller is configured to control operations of the virtual division memory, the stream shift buffer, and the decoder circuit.

Abstract: An emulation prevention byte remover may include one or more of a first buffer, a second buffer, a checker, and a shifter. The first buffer may store first stream data. The second buffer may store second stream data. The checker may determine whether one or more emulation prevention bytes are included in the first, second, or first and second stream data. If the checker determines that the one or more emulation prevention bytes are included in the first, second, or first and second stream data, the checker may output a check signal. In response to the check signal, the shifter may remove at least one of the one or more emulation prevention bytes from the first, second, or first and second stream data. The shifter may generate output stream data based on the first, second, or first and second stream data.

Abstract: A bit stream processing device may include a virtual division memory, a stream shift buffer, a decoder circuit, and a controller. The virtual division memory may be divided into a plurality of group memory regions configured to store a plurality of stream groups in the respective group memory regions and to output a memory bit stream. The stream groups may be included in an input bit stream. The stream shift buffer is configured to receive and store the memory bit stream and output a buffer bit stream. The decoder circuit is configured to perform a decoding operation on the buffer bit stream from the stream shift buffer. The controller is configured to control operations of the virtual division memory, the stream shift buffer, and the decoder circuit.

Abstract: An apparatus processing a video stream includes a CPU, a memory access controller reading stream data from an external memory, a buffer storing the stream data, and a hardware accelerator decoding the stream data. The hardware accelerator includes a plurality of decoders decoding the stream data in accordance with one of a plurality of different video coding standards.

Abstract: An apparatus processing a video stream includes a CPU, a memory access controller reading stream data from an external memory, a buffer storing the stream data, and a hardware accelerator decoding the stream data. The hardware accelerator includes a plurality of decoders decoding the stream data in accordance with one of a plurality of different video coding standards.

Abstract: An apparatus processing a video stream includes a CPU, a memory access controller reading stream data from an external memory, a buffer storing the stream data, and a hardware accelerator decoding the stream data. The hardware accelerator includes a plurality of decoders decoding the stream data in accordance with one of a plurality of different video coding standards.

Abstract: According to a coefficient variable length coding method adopting four-stage pipeline, a 3-dimension value including a run, a level and a last data is obtained by performing a run length coding upon coefficient data, where, after transferring the 3-dimension value, a variable bit vector is obtained from the transferred 3-dimension value and the variable length bit vector is stored, and where, particularly in case the pipeline breaks, the method reuses the previously obtained 3-dimension value to minimize process time such that the coefficient variable length coding is swiftly performed by the efficient pipeline operation, and the broken pipeline may be restored within minimized time.

Abstract: An apparatus processing a video stream includes a CPU, a memory access controller reading stream data from an external memory, a buffer storing the stream data, and a hardware accelerator decoding the stream data. The hardware accelerator includes a plurality of decoders decoding the stream data in accordance with one of a plurality of different video coding standards.

Abstract: An emulation prevention byte remover may include one or more of a first buffer, a second buffer, a checker, and a shifter. The first buffer may store first stream data. The second buffer may store second stream data. The checker may determine whether one or more emulation prevention bytes are included in the first, second, or first and second stream data. If the checker determines that the one or more emulation prevention bytes are included in the first, second, or first and second stream data, the checker may output a check signal. In response to the check signal, the shifter may remove at least one of the one or more emulation prevention bytes from the first, second, or first and second stream data. The shifter may generate output stream data based on the first, second, or first and second stream data.

Abstract: A context-adaptive variable length coding (VLC) apparatus includes a coefficient information generation unit configured to generate coefficient information used for coding variable-length-code coefficients for a selected block of a selected macroblock of image data that is read out in response to an information generation control signal, a bit data generation unit configured to operate in response to a bit generation control signal, and to code coefficients of a previous block, which is read out just before the selected block, using coefficient information of the previous block, and a control unit configured to generate the information generation control signal and the bit generation control signal, and to cause the coefficient information generation unit and the bit data generation unit to operate at in parallel using the information generation control signal and the bit generation control signal. A method of variable-length coding coefficients of image data is also provided.

Abstract: According to a coefficient variable length coding method adopting four-stage pipeline, a 3-dimension value including a run, a level and a last data is obtained by performing a run length coding upon coefficient data, where, after transferring the 3-dimension value, a variable bit vector is obtained from the transferred 3-dimension value and the variable length bit vector is stored, and where, particularly in case the pipeline breaks, the method reuses the previously obtained 3-dimension value to minimize process time such that the coefficient variable length coding is swiftly performed by the efficient pipeline operation, and the broken pipeline may be restored within minimized time.