Patents by Inventor Kyung-Lyul Moon
Kyung-Lyul Moon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10712662Abstract: A method of forming a pattern is disclosed. The method includes preparing a composition that includes a solvent and a polymer including a repeating unit in which at least one isocyanurate unit having a first structure is connected to another isocyanurate unit having a second structure different from the first structure; applying the composition on a substrate to form an underlayer; forming a photoresist layer on the underlayer; etching the photoresist layer to form a photoresist pattern; and patterning the substrate using the photoresist pattern.Type: GrantFiled: January 13, 2017Date of Patent: July 14, 2020Assignees: SAMSUNG ELECTRONICS CO., LTD., DONGJIN SEMICHEM CO., LTD.Inventors: Jin-A Ryu, Jung-Youl Lee, Kyung-Lyul Moon, Yool Kang, Hyun-Jin Kim, Yu-Jin Jeoung, Man-Ho Han
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Publication number: 20170199459Abstract: A method of forming a pattern is disclosed. The method includes preparing a composition that includes a solvent and a polymer including a repeating unit in which at least one isocyanurate unit having a first structure is connected to another isocyanurate unit having a second structure different from the first structure; applying the composition on a substrate to form an underlayer; forming a photoresist layer on the underlayer; etching the photoresist layer to form a photoresist pattern; and patterning the substrate using the photoresist pattern.Type: ApplicationFiled: January 13, 2017Publication date: July 13, 2017Inventors: Jin-A RYU, Jung-Youl LEE, Kyung-Lyul MOON, Yool KANG, Hyun-Jin KIM, Yu-Jin JEOUNG, Man-Ho HAN
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Patent number: 9099470Abstract: Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed.Type: GrantFiled: March 13, 2014Date of Patent: August 4, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Ho Lee, Jae-Hwang Sim, Sang-Yong Park, Kyung-Lyul Moon
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Patent number: 9093454Abstract: In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region.Type: GrantFiled: February 21, 2014Date of Patent: July 28, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Yong Park, Jae-Hwang Sim, Young-Ho Lee, Kyung-Lyul Moon, Jae-Kwan Park
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Publication number: 20140191405Abstract: Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed.Type: ApplicationFiled: March 13, 2014Publication date: July 10, 2014Inventors: Young-Ho Lee, Jae-Hwang Sim, Sang-Yong Park, Kyung-Lyul Moon
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Publication number: 20140167290Abstract: In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region.Type: ApplicationFiled: February 21, 2014Publication date: June 19, 2014Inventors: Sang-Yong Park, Jae-Hwang Sim, Young-Ho Lee, Kyung-Lyul Moon, Jae-Kwan Park
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Patent number: 8697580Abstract: Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed.Type: GrantFiled: November 16, 2012Date of Patent: April 15, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Ho Lee, Jae-Hwang Sim, Sang-Yong Park, Kyung-Lyul Moon
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Patent number: 8686563Abstract: In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region.Type: GrantFiled: December 16, 2009Date of Patent: April 1, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Yong Park, Jae-Hwang Sim, Young-Ho Lee, Kyung-Lyul Moon, Jae-Kwan Park
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Publication number: 20130072022Abstract: Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed.Type: ApplicationFiled: November 16, 2012Publication date: March 21, 2013Inventors: Young-Ho Lee, Jae-Hwang Sim, Sang-Yong Park, Kyung-Lyul Moon
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Patent number: 8318603Abstract: Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed.Type: GrantFiled: December 16, 2009Date of Patent: November 27, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Ho Lee, Jae-Hwang Sim, Sang-Yong Park, Kyung-Lyul Moon
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Patent number: 8057692Abstract: In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region.Type: GrantFiled: October 30, 2008Date of Patent: November 15, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Yong Park, Jae-Hwang Sim, Young-Ho Lee, Kyung-Lyul Moon, Jae-Kwan Park
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Publication number: 20100221919Abstract: Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed.Type: ApplicationFiled: December 16, 2009Publication date: September 2, 2010Applicant: Samsung Electronics Co., Ltd.Inventors: Young-Ho Lee, Jae-Hwang Sim, Sang-Yong Park, Kyung-Lyul Moon
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Publication number: 20100090349Abstract: In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region.Type: ApplicationFiled: December 16, 2009Publication date: April 15, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Yong Park, Jae-Hwang Sim, Young-Ho Lee, Kyung-Lyul Moon, Jae-Kwan Park
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Publication number: 20090311861Abstract: In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region.Type: ApplicationFiled: October 30, 2008Publication date: December 17, 2009Applicant: Samsung Electronics Co., Ltd.Inventors: Sang-Yong Park, Jae-Hwang Sim, Young-Ho Lee, Kyung-Lyul Moon, Jae-Kwan Park