Abstract: A display device comprises a display area comprising a plurality of pixels, and a data line and a gate line electrically connected to the plurality of pixels, a non-display area disposed adjacent to the display area, a plurality of pads disposed on a side of the non-display area, a gate control line electrically connected to at least one of the plurality of pads and that supplies a gate control signal, a driving voltage line electrically connected to at least one of the plurality of pads and that supplies a driving voltage, an antistatic circuit electrically connected to the gate control line, a scan driver that generates a gate signal based on a gate control signal received from the gate control line and that supplies the gate signal to the gate line, and a shielding layer integral to the driving voltage line to overlap the top of the antistatic circuit.

Abstract: A semiconductor device includes a plurality of wiring structures spaced apart from each other, and an insulating interlayer structure. Each of the wiring structures includes a metal pattern and a barrier pattern covering a sidewall, a bottom surface, and an edge portion of a top surface of the metal pattern and not covering a central portion of the top surface of the metal pattern. The insulating interlayer structure contains the wiring structures therein, and has an air gap between the wiring structures.

Abstract: The present invention relates to a cage device inserted between adjacent vertebral bodies to be used for anterior vertebral body fusion. The cage device includes: a cage; and a staple fixing the cage between adjacent vertebral bodies, in which the staple is configured to include an upper fixed arm extending toward a back surface of the cage while being spaced apart from an upper surface of the cage, a lower fixed arm extending toward the back surface of the cage while being spaced apart from a lower surface of the cage, and a support part fixing the fixed arms to a front surface of the cage and ruggedness is formed on any one of upper and lower surfaces of the upper fixed arm 22 and the lower fixed arm 23.

Abstract: A semiconductor device includes a plurality of wiring structures spaced apart from each other, and an insulating interlayer structure. Each of the wiring structures includes a metal pattern and a barrier pattern covering a sidewall, a bottom surface, and an edge portion of a top surface of the metal pattern and not covering a central portion of the top surface of the metal pattern. The insulating interlayer structure contains the wiring structures therein, and has an air gap between the wiring structures.

Abstract: A phase-change memory device includes a diode, a plug, a doping layer pattern, a phase-change layer pattern and an upper electrode. The diode is disposed on a substrate. The plug is disposed on the diode and has a bottom surface whose area is equal to the area of a top surface of the diode. The plug is formed of metal or a conductive metallic compound. The doping layer pattern is disposed on the plug and has a bottom surface whose area is equal to the area of a top surface of the plug, and includes the same metal or conductive metallic compound as the plug. The phase-change layer pattern is disposed on the doping layer pattern. The upper electrode is disposed on the phase-change layer pattern.

Abstract: A method of manufacturing the semiconductor device includes sequentially forming first to third mold layer patterns on a substrate and spaced apart from each other, forming a first semiconductor pattern between the first mold layer pattern and the second mold layer pattern, and a second semiconductor pattern between the second mold layer pattern and the third mold layer pattern, forming a first trench between the first mold layer pattern and the third mold layer pattern by removing a portion of the second mold layer pattern and portions of the first and second semiconductor patterns, depositing a material for a lower electrode conformally along side and bottom surfaces of the first trench, and forming first and second lower electrodes separated from each other on the first and second semiconductor patterns, respectively, by removing a portion of the material for a lower electrode positioned on the second mold layer pattern.

Abstract: A phase-change memory device includes a word line on a substrate and a phase-change memory cell on the word line and comprising a phase-change material pattern. The device also includes a non-uniform conductivity layer pattern comprising a conductive region on the phase-change material pattern and a non-conductive region contiguous therewith. The device further includes a bit line on the conductive region of the non-uniform conductivity layer pattern. In some embodiments, the phase-change memory cell may further include a diode on the word line, a heating electrode on the diode and wherein the phase-change material layer is disposed on the heating electrode. An ohmic contact layer and a contact plug may be disposed between the diode and the heating electrode.

Abstract: A phase-change memory device includes a diode, a plug, a doping layer pattern, a phase-change layer pattern and an upper electrode. The diode is disposed on a substrate. The plug is disposed on the diode and has a bottom surface whose area is equal to the area of a top surface of the diode. The plug is formed of metal or a conductive metallic compound. The doping layer pattern is disposed on the plug and has a bottom surface whose area is equal to the area of a top surface of the plug, and includes the same metal or conductive metallic compound as the plug. The phase-change layer pattern is disposed on the doping layer pattern. The upper electrode is disposed on the phase-change layer pattern.

Abstract: Memory devices and methods of forming memory devices including forming a plurality of preliminary electrodes, each of the plurality of preliminary electrodes including a protruding region, protruding from a first mold insulating layer, forming a second mold insulating layer on the first mold insulating layer, removing at least a portion of the plurality of preliminary electrodes to form a plurality of openings in the second mold insulating layer and a plurality of lower electrodes, and forming a plurality of memory elements in the plurality of openings. Memory devices and methods of forming memory devices including forming one or more insulating layers on sidewalls of all or part of a plurality of lower electrodes and/or a plurality of memory elements.

Abstract: A phase-change memory device includes a word line on a substrate and a phase-change memory cell on the word line and comprising a phase-change material pattern. The device also includes a non-uniform conductivity layer pattern comprising a conductive region on the phase-change material pattern and a non-conductive region contiguous therewith. The device further includes a bit line on the conductive region of the non-uniform conductivity layer pattern. In some embodiments, the phase-change memory cell may further include a diode on the word line, a heating electrode on the diode and wherein the phase-change material layer is disposed on the heating electrode. An ohmic contact layer and a contact plug may be disposed between the diode and the heating electrode.

Abstract: Memory devices and methods of forming memory devices including forming a plurality of preliminary electrodes, each of the plurality of preliminary electrodes including a protruding region, protruding from a first mold insulating layer, forming a second mold insulating layer on the first mold insulating layer, removing at least a portion of the plurality of preliminary electrodes to form a plurality of openings in the second mold insulating layer and a plurality of lower electrodes, and forming a plurality of memory elements in the plurality of openings. Memory devices and methods of forming memory devices including forming one or more insulating layers on sidewalls of all or part of a plurality of lower electrodes and/or a plurality of memory elements.

Abstract: A method of fabricating an integrated circuit device includes forming first and second patterns extending in first and second directions, respectively, on a target layer. The first patterns comprise a metal oxide and/or metal silicate material having an etch selectivity with respect to that of the target layer. The second patterns comprise a material having an etch selectivity with respect to those of the first patterns and the target layer. The target layer is selectively etched using the first patterns and the second patterns as an etch mask to define holes respectively extending through the target layer to expose a layer therebelow. At least one of the first and second patterns is formed using respective mask patterns formed by a photolithographic process, and the at least one of the first and second patterns have a finer pitch than that of the respective mask patterns.

Abstract: A method of manufacturing the semiconductor device includes sequentially forming first to third mold layer patterns on a substrate and spaced apart from each other , forming a first semiconductor pattern between the first mold layer pattern and the second mold layer pattern, and a second semiconductor pattern between the second mold layer pattern and the third mold layer pattern, forming a first trench between the first mold layer pattern and the third mold layer pattern by removing a portion of the second mold layer pattern and portions of the first and second semiconductor patterns, depositing a material for a lower electrode conformally along side and bottom surfaces of the first trench, and forming first and second lower electrodes separated from each other on the first and second semiconductor patterns, respectively, by removing a portion of the material for a lower electrode positioned on the second mold layer pattern.

Abstract: A method of manufacturing a nonvolatile memory device includes forming an insulating film pattern, which includes apertures, on a substrate, forming a switching element in each of the apertures, forming a bottom electrode on the switching element by using a silicon (Si)-doped titanium nitride (TiN) film, and forming a variable resistance material pattern on the bottom electrode. The Si-doped TiN film is formed by repeatedly forming a TiN film and doping the TiN film with Si.

Abstract: Provided is a plasma flat lamp. The provided lamp includes a discharge gas filled in a discharge area of a discharge container, at least two electrodes generating a gas discharge in the discharge area, a low work function material layer located in a discharge path between the electrodes and collided against gas ions that are generated by the gas discharge, and a fluorescent layer generating visible rays by ultraviolet rays that are generated by the gas discharge in the discharge container. The provided plasma flat lamp reduces a driving voltage due to the low work function material layer against which ions are collided, and increases luminescent efficiency by reducing the absorption of ultraviolet rays of the low work function material layer.

Abstract: A plasma discharge method and a plasma display using the same. In the method, a sustain discharge uses a facing surfaces discharge and a surface discharge after an address discharge. The discharges occur in separate discharge areas, and priming particles generated by the discharges are exchanged. Thus, the stability and the efficiency of the sustain discharge increase, and a gap for the address discharge decreases to lower a breakdown voltage.

Abstract: Provided is a plasma flat lamp. The provided lamp includes a discharge gas filled in a discharge area of a discharge container, at least two electrodes generating a gas discharge in the discharge area, a low work function material layer located in a discharge path between the electrodes and collided against gas ions that are generated by the gas discharge, and a fluorescent layer generating visible rays by ultraviolet rays that are generated by the gas discharge in the discharge container. The provided plasma flat lamp reduces a driving voltage due to the low work function material layer against which ions are collided, and increases luminescent efficiency by reducing the absorption of ultraviolet rays of the low work function material layer.

Abstract: A plasma discharge method and a plasma display using the same. In the method, a sustain discharge uses a facing surfaces discharge and a surface discharge after an address discharge. The discharges occur in separate discharge areas, and priming particles generated by the discharges are exchanged. Thus, the stability and the efficiency of the sustain discharge increase, and a gap for the address discharge decreases to lower a breakdown voltage.

Abstract: A plasma lamp includes a container filled with a discharge gas, a main discharge electrode unit located in the container and including a first electrode and a second electrode, which define a main discharge region of a first gap and generate a main discharge, and a preliminary discharge electrode unit having a high resistance unit and arranged on at least one of the first electrode and the second electrode, and located adjacent to the main discharge region to define a preliminary discharge region of a second gap, which is smaller than the first gap. The preliminary discharge electrode unit of the provided plasma lamp induces a preliminary discharge for a short time at a low voltage. A main discharge occurs conveniently due to charged particles generated by the preliminary discharge.