Abstract: A semiconductor memory device includes a refresh counter generating a counting address that is sequentially increasing according to a refresh command; an active latch generating an active address corresponding to an input address according to an active command; and a refresh control circuit repeatedly performing a first refresh period and a second refresh period according to the refresh command, and controlling selective refresh of one or more word lines corresponding to the counting address selected based on one or more high bits of the active address during the first refresh period and controlling sequential refresh of the word lines corresponding to the counting address during the second refresh period.

Abstract: An electronic device includes a command generation circuit configured to generate a refresh command and a driving control signal, which are enabled during an all-bank refresh operation, according to a logic level combination of an internal chip selection signal and an internal command address. The electronic device also includes a buffer control circuit configured to generate, from the refresh command and the driving control signal, a first buffer enable signal for enabling a first group of buffers and a second buffer enable signal for enabling a second group of buffers.

Abstract: An electronic device includes a shifting circuit and a dock repeater. The shifting circuit is configured to generate a write shifting flag that is inactivated when a write signal for a write operation is activated. The clock repeater is configured to block generation of a read repeating dock that is used in a read operation when the write shifting flag is inactivated.

Abstract: An electronic device includes a command generation circuit configured to generate a refresh command and a driving control signal, which are enabled during an all-bank refresh operation, according to a logic level combination of an internal chip selection signal and an internal command address. The electronic device also includes a buffer control circuit configured to generate, from the refresh command and the driving control signal, a first buffer enable signal for enabling a first group of buffers and a second buffer enable signal for enabling a second group of buffers.

Abstract: An electronic device includes a command generation circuit configured to generate a refresh command and a driving control signal, which are enabled during an all-bank refresh operation, according to a logic level combination of an internal chip selection signal and an internal command address. The electronic device also includes a buffer control circuit configured to generate, from the refresh command and the driving control signal, a first buffer enable signal for enabling a first group of buffers and a second buffer enable signal for enabling a second group of buffers.

Abstract: A device includes an operation control circuit and a drive control signal generation circuit. The operation control circuit generates an internal refresh signal that is activated to perform an active operation for a cell array, the cell array being coupled to a word line that is selected by a row address based on a refresh signal that is activated to perform a refresh operation. In addition, the operation control circuit generates a pre-refresh pulse based on the refresh signal and generates a refresh end pulse based on the internal refresh signal. The drive control signal generation circuit generates a drive control signal to control a drive of an active voltage that is supplied to the word line that is selected by the row address based on the internal refresh signal, the pre-refresh pulse, and the refresh end pulse.

Abstract: A device for performing a refresh operation includes a row control circuit and a row decoder. The row control circuit is configured to generate a bank active signal and a row address for controlling an active operation for a first memory bank based on a refresh signal. The row control circuit is also configured to generate the bank active signal for controlling the active operation for a second memory bank based on a power control signal. The row decoder is configured to receive the bank active signal and the row address to control the active operation for the first memory bank and the second memory bank.

Abstract: A semiconductor device includes an internal column control signal generation circuit, a bank address transfer circuit, and a first bank control circuit. The internal column control signal generation circuit generates a column control signal to output an internal column control signal. The bank address transfer circuit receives a bank address to generate an inverted bank address and outputs the bank address and the inverted bank address. The first bank control circuit generates a first bank active signal based on at least one of the bank address and the inverted bank address and latches the first bank active signal based on the internal column control signal to generate a first bank column control signal.

Abstract: A device includes an operation control circuit and a drive control signal generation circuit. The operation control circuit generates an internal refresh signal that is activated to perform an active operation for a cell array, the cell array being coupled to a word line that is selected by a row address based on a refresh signal that is activated to perform a refresh operation. In addition, the operation control circuit generates a pre-refresh pulse based on the refresh signal and generates a refresh end pulse based on the internal refresh signal. The drive control signal generation circuit generates a drive control signal to control a drive of an active voltage that is supplied to the word line that is selected by the row address based on the internal refresh signal, the pre-refresh pulse, and the refresh end pulse.

Abstract: An electronic device includes a command generation circuit configured to generate a refresh command and a driving control signal, which are enabled during an all-bank refresh operation, according to a logic level combination of an internal chip selection signal and an internal command address. The electronic device also includes a buffer control circuit configured to generate, from the refresh command and the driving control signal, a first buffer enable signal for enabling a first group of buffers and a second buffer enable signal for enabling a second group of buffers.

Abstract: An electronic device includes a shifting circuit and a dock repeater. The shifting circuit is configured to generate a write shifting flag that is inactivated when a write signal for a write operation is activated. The clock repeater is configured to block generation of a read repeating dock that is used in a read operation when the write shifting flag is inactivated.

Abstract: A device for performing a refresh operation includes a row control circuit and a row decoder. The row control circuit is configured to generate a bank active signal and a row address for controlling an active operation for a first memory bank based on a refresh signal. The row control circuit is also configured to generate the bank active signal for controlling the active operation for a second memory bank based on a power control signal. The row decoder is configured to receive the bank active signal and the row address to control the active operation for the first memory bank and the second memory bank.

Abstract: A semiconductor memory device includes: a plurality of banks each suitable for refreshing at least one word line corresponding to a refresh address according to a row active signal; a refresh control circuit suitable for controlling, in response to a refresh command, an activation timing of the row active signal according to mode signals and a counting signal; a refresh counter suitable for generating the counting signal by counting the number of times the row active signal is activated, and generating sequence signals which are sequentially activated; and a detection circuit suitable for generating flag signals by combining the sequence signals, and generating a detection signal according to a corresponding one of the flag signals when any of the mode signals is activated, wherein the refresh counter is initialized by the detection signal.

Abstract: A semiconductor device includes an internal column control signal generation circuit, a bank address transfer circuit, and a first bank control circuit. The internal column control signal generation circuit generates a column control signal to output an internal column control signal. The bank address transfer circuit receives a bank address to generate an inverted bank address and outputs the bank address and the inverted bank address. The first bank control circuit generates a first bank active signal based on at least one of the bank address and the inverted bank address and latches the first bank active signal based on the internal column control signal to generate a first bank column control signal.

Abstract: A semiconductor device includes a flag shifting circuit and an auto-pre-charge control circuit. The flag shifting circuit generates a first shifted flag signal by shifting a first flag signal by a second latency period, the first flag signal generated based on a first operation clock signal, and configured to generate a second shifted flag signal by shifting a second flag signal by a first latency period, the second flag signal generated based on a second operation clock signal. The auto-pre-charge control circuit generates an auto-pre-charge signal by shifting the first shifted flag signal and the second shifted flag signal by a recovery period based on the first operation clock signal and the second operation clock signal.

Abstract: A semiconductor device includes a shift control circuit and a synthesis pre-charge signal generation circuit. The shift control circuit generates a shift signal and a shift read signal based on a read command and controls a reset status of the shift read signal based on the shift signal and an auto-pre-charge command. The synthesis pre-charge signal generation circuit generates a synthesis pre-charge signal for an auto-pre-charge operation of a bank selected by an address based on the shift read signal and the address.

Abstract: A semiconductor memory device includes: a plurality of banks each suitable for refreshing at least one word line corresponding to a refresh address according to a row active signal; a refresh control circuit suitable for controlling, in response to a refresh command, an activation timing of the row active signal according to mode signals and a counting signal; a refresh counter suitable for generating the counting signal by counting the number of times the row active signal is activated, and generating sequence signals which are sequentially activated; and a detection circuit suitable for generating flag signals by combining the sequence signals, and generating a detection signal according to a corresponding one of the flag signals when any of the mode signals is activated, wherein the refresh counter is initialized by the detection signal.

Abstract: A semiconductor device includes a variable delay circuit and an address latch circuit. The variable delay circuit delays a read signal by a delay time to generate a latch control signal during an initialization operation and receives a feedback signal to adjust the delay time for delaying the read signal during the initialization operation. The address latch circuit detects a logic level of a transfer address when the latch control signal is inputted to the address latch circuit and generates the feedback signal.

Abstract: A memory device includes a target clock generation circuit suitable for generating a target clock by dividing a frequency of an internal clock at a set ratio, a delay circuit suitable for generating first to Nth delay clocks having first to Nth pulse widths that gradually increase, in synchronization with the target clock, a flag detection circuit suitable for filtering the first to Nth delay clocks based on the target clock to generate first to Nth flag signals and decoding the first to Nth flag signals to generate first to (N?1)th current control signals, and a buffer circuit suitable for adjusting an amount of current based on the first to (N?1)th current control signals, and buffering an externally inputted signal using the adjusted amount of current.

Abstract: A memory device includes a target clock generation circuit suitable for generating a target clock by dividing a frequency of an internal clock at a set ratio, a delay circuit suitable for generating first to Nth delay clocks having first to Nth pulse widths that gradually increase, in synchronization with the target clock, a flag detection circuit suitable for filtering the first to Nth delay clocks based on the target clock to generate first to Nth flag signals and decoding the first to Nth flag signals to generate first to (N?1)th current control signals, and a buffer circuit suitable for adjusting an amount of current based on the first to (N?1)th current control signals, and buffering an externally inputted signal using the adjusted amount of current.