Abstract: A switching mode power supply includes a rectifier configured to convert AC power to a first DC power, an output unit configured to convert the first DC power to a second DC power under the control of a first switch, and a pulse width modulation generator coupled to control the first switch. The pulse width modulation generator has a regulator configured to regulate the first DC power. The regulated first DC power powers the pulse width modulation generator. The regulator includes a second switch coupled to control a transmitter so that when the second switch is in a first state the transmitter transmits the first DC power to a capacitor to charge the capacitor to thereby increase the regulated first DC power, and when the switch is in a second state the transmitter does not transmit the first DC power to the capacitor to thereby allow the charge in the capacitor to reduce and in turn the regulated first DC power to reduce.

Abstract: A CMOS transistor is provided having a relatively high breakdown voltage. The CMOS transistor includes an N-type epitaxial layer on a P-type substrate. Between the substrate and epitaxial layer are a heavily doped N-type buried layer and a heavily doped P-type base layer. An N-type sink region is proximate the edge of the NMOS region, and twin wells are in the area surrounded with the sink region. N+ source and drain regions are formed in respective wells. As the sink region is interposed between the drain and isolation regions, a breakdown occurs between the sink and isolation regions when a high voltage is applied. Twin wells are also formed in the PMOS region. P+ source and drain regions are formed in respective wells. As the N-type well surrounds the source and bulk regions, a breakdown occurs between a buried region and the isolation region when a high voltage is applied.

Abstract: In accordance with an embodiment of the invention, a switching mode power supply includes a rectifier configured to convert AC power to a first DC power, an output unit configured to convert the first DC power to a second DC power under the control of a first switch, and a pulse width modulation generator coupled to control the first switch. The pulse width modulation generator has a regulator configured to regulate the first DC power. The regulated first DC power powers the pulse width modulation generator. The regulator includes a second switch coupled to control a transmitter so that when the second switch is in a first state the transmitter transmits the first DC power to a capacitor to charge the capacitor, and when the switch is in a second state the transmitter does not transmit the first DC power to the capacitor to thereby allow the charge in the capacitor to reduce.

Abstract: In an EMI canceller, a control signal generation unit includes a counter, a second flip-flop, and a multiplexer. The counter outputs first and second output signals and includes first flip-flops in series. An output of the first flip-flop reverses at every cycle of the first and second output signals of a previous first flip-flop. An output of the second flip-flop reverses at every cycle of the first or second output signal of a final first flip-flop. The second flip-flop outputs third and fourth output signals. The multiplexer passes the first output signals of the first flip-flop as a control signal when the third output signal is a first level, and passes the second output signals as the control signal when it is a second level.

Abstract: A CMOS transistor is provided having a relatively high breakdown voltage. The CMOS transistor includes an N-type epitaxial layer on a P-type substrate. Between the substrate and epitaxial layer are a heavily doped N-type buried layer and a heavily doped P-type base layer. An N-type sink region is proximatethe edge of the NMOS region, and twin wells are in the area surrounded with the sink region. N+ source and drain regions are formed in respective wells. As the sink region is interposed between the drain and isolation regions, a breakdown occurs between the sink and isolation regions when a high voltage is applied. Twin wells are also formed in the PMOS region . P+ source and drain regions are formed in respective wells. As the N-type well surrounds the source and bulk regions, a breakdown occurs between a buried region and the isolation region when a high voltage is applied.

Abstract: A CMOS transistor is provided having a relatively high breakdown voltage. The CMOS transistor includes an N-type epitaxial layer on a P-type substrate. Between the substrate and epitaxial layer are a heavily doped N-type buried layer and a heavily doped P-type base layer. An N-type sink region is proximatethe edge of the NMOS region, and twin wells are in the area surrounded with the sink region. N+ source and drain regions are formed in respective wells. As the sink region is interposed between the drain and isolation regions, a breakdown occurs between the sink and isolation regions when a high voltage is applied. Twin wells are also formed in the PMOS region P+ source and drain regions are formed in respective wells. As the N-type well surrounds the source and bulk regions, a breakdown occurs between a buried region and the isolation region when a high voltage is applied.

Abstract: A high efficiency switching controller for use in a switching power supply (SPS) includes a current control device coupled to a voltage source of the SPS and a switch connected between the current control device and an output voltage circuit of the SPS. An under voltage lockout regulator coupled to the output voltage circuit of the SPS and the switch controls the state of the switch based on a voltage of the output voltage circuit and a bias unit coupled to the under voltage lockout regulator provides current to circuitry within the switching controller based on the voltage of the output voltage circuit. A protector within the high efficiency switching controller provides a control signal to the pulse width modulator unit to control the gate drive signal in response to an operating condition of the switching controller.

Abstract: A CMOS transistor is provided having a relatively high breakdown voltage. The CMOS transistor includes an N-type epitaxial layer on a P-type substrate. Between the substrate and epitaxial layer are a heavily doped N-type buried layer and a heavily doped P-type base layer. An N-type sink region is proximate the edge of the NMOS region, and twin wells are in the area surrounded with the sink region. N+ source and drain regions are formed in respective wells. As the sink region is interposed between the drain and isolation regions, a breakdown occurs between the sink and isolation regions when a high voltage is applied. Twin wells are also formed in the PMOS region P+ source and drain regions are formed in respective wells. As the N-type well surrounds the source and bulk regions, a breakdown occurs between a buried region and the isolation region when a high voltage is applied.

Abstract: A switching power supply having a high efficiency starting circuit uses a field effect transistor to provide initial starting current to a pulse width modulated signal generator within a switching control circuit. The field effect transistor (FET) has a drain connected to a source of supply voltage, a source connected to the PWM signal generator, and a gate connected to a feedback voltage that is derived from an output voltage of the switching power supply. During start up of the switching power supply, the FET provides current to the PWM signal generator. When the feedback voltage reaches a predetermined level, the FET supplies substantially near zero current to the PWM signal generator, thereby eliminating the electrical inefficiencies typically associated with a conventional switching power supply starting circuit.