Patents by Inventor Kyung Pil Hwang
Kyung Pil Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110204430Abstract: A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.Type: ApplicationFiled: April 29, 2011Publication date: August 25, 2011Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Se Jun KIM, Eun Seok CHOI, Kyoung Hwan PARK, Hyun Seung YOO, Myung Shik LEE, Young Ok HONG, Jung Ryul AHN, Yong Top KIM, Kyung Pil HWANG, Won Sic WOO, Jae Young PARK, Ki Hong LEE, Ki Seon PARK, Moon Sig JOO
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Patent number: 7990771Abstract: A method of erasing and programming a flash memory device including multi-level cells (MLCs). MLCs of a word line are selected and some of the MLCs are pre-programmed based on whether their individual threshold voltages are included in a first voltage range. The selected MLCs are pre-programmed with a pre-program (first) voltage; and the remaining MLCs are prohibited from pre-programming; then the remaining MLCs connected to the selected word line are programmed by applying a program (second) voltage that gradually rises from the pre-program voltage at a ratio of a step voltage n for the selected line.Type: GrantFiled: April 16, 2009Date of Patent: August 2, 2011Assignee: Hynix Semiconductor Inc.Inventors: Kyung Pil Hwang, Hyung Seok Kim, Keum Hwan Noh, Ju In Kim, Min Kyu Lee, Seok Jin Joo, Sook Kyung Kim
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Patent number: 7978532Abstract: Erase and program methods of a flash memory device including MLCs for increasing the program speed. In the erase method, MLCs are pre-programmed so that a voltage range in which threshold voltages of MLCs are distributed can be reduced. Therefore, a fail occurrence ratio can be reduced when erasing MLCs, the threshold voltage distribution of MLCs can be improved and an overall program time can be shortened in a subsequent program operation.Type: GrantFiled: April 16, 2009Date of Patent: July 12, 2011Assignee: Hynix Semiconductor Inc.Inventors: Kyung Pil Hwang, Hyung Seok Kim, Keum Hwan Noh, Ju In Kim, Min Kyu Lee, Seok Jin Joo, Sook Kyung Kim
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Patent number: 7955960Abstract: A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.Type: GrantFiled: March 21, 2008Date of Patent: June 7, 2011Assignee: Hynix Semiconductor Inc.Inventors: Se Jun Kim, Eun Seok Choi, Kyoung Hwan Park, Hyun Seung Yoo, Myung Shik Lee, Young Ok Hong, Jung Ryul Ahn, Yong Top Kim, Kyung Pil Hwang, Won Sic Woo, Jae Young Park, Ki Hong Lee, Ki Seon Park, Moon Sig Joo
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Patent number: 7715233Abstract: A non-volatile memory device is provided. In an aspect, the non-volatile memory device includes two or more common source lines that are included in one memory cell block in order to distribute the current that could have been concentrated on one common source line. As a result, the bouncing phenomenon generated by the nose of the source line can be reduced. That is, at the time of a verifying operation performed during a program operation, the current concentrated on a common source line can be distributed and, therefore, the occurrence of under-programmed cells can be prevented.Type: GrantFiled: March 7, 2008Date of Patent: May 11, 2010Assignee: Hynix Semiconductor Inc.Inventors: Kyung Pil Hwang, Won Sic Woo
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Patent number: 7701768Abstract: A method for programming an MLC flash memory device minimizes interference between adjacent cells during a program operation, such that threshold voltage distribution becomes narrow and uniform. According to the method, an auxiliary program operation is performed on memory cells to be programmed, such that a majority of the memory cells have a positive threshold voltage. An LSB of a particular memory cell is programmed to a predetermined level, and data of the programmed LSB is sensed. An MSB of the particular memory cell is programmed to a predetermined level according to the sensed data of the LSB.Type: GrantFiled: December 28, 2007Date of Patent: April 20, 2010Assignee: Hynix Semiconductor Inc.Inventor: Kyung-Pil Hwang
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Publication number: 20090207660Abstract: Erase and program methods of a flash memory device including MLCs for increasing the program speed are described. In the erase method, MLCs are pre-programmed so that a voltage range in which threshold voltages of MLCs are distributed can be reduced. Therefore, a fail occurrence ratio can be reduced when erasing MLCs, the threshold voltage distribution of MLCs can be improved and an overall program time can be shortened in a subsequent program operation.Type: ApplicationFiled: April 16, 2009Publication date: August 20, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Kyung Pil Hwang, Hyung Seok Kim, Keum Hwan Noh, Ju In Kim, Min Kyu Lee, Seok Jin Joo, Sook Kyung Kim
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Publication number: 20090201728Abstract: Erase and program methods of a flash memory device including MLCs for increasing the program speed are described. In the erase method, MLCs are pre-programmed so that a voltage range in which threshold voltages of MLCs are distributed can be reduced. Therefore, a fail occurrence ratio can be reduced when erasing MLCs, the threshold voltage distribution of MLCs can be improved and an overall program time can be shortened in a subsequent program operation.Type: ApplicationFiled: April 16, 2009Publication date: August 13, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Kyung Pil Hwang, Hyung Seok Kim, Keum Hwan Noh, Ju In Kim, Min Kyu Lee, Seok Jin Joo, Sook Kyung Kim
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Patent number: 7539057Abstract: Erase and program methods of a flash memory device including MLCs for increasing the program speed are described. In the erase method, MLCs are pre-programmed so that a voltage range in which threshold voltages of MLCs are distributed can be reduced. Therefore, a fail occurrence ratio can be reduced when erasing MLCs, the threshold voltage distribution of MLCs can be improved and an overall program time can be shortened in a subsequent program operation.Type: GrantFiled: December 21, 2005Date of Patent: May 26, 2009Assignee: Hynix Semiconductor Inc.Inventors: Kyung Pil Hwang, Hyung Seok Kim, Keum Hwan Noh, Ju In Kim, Min Kyu Lee, Seok Jin Joo, Sook Kyung Kim
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Publication number: 20090003055Abstract: A method for programming an MLC flash memory device minimizes interference between adjacent cells during a program operation, such that threshold voltage distribution becomes narrow and uniform. According to the method, an auxiliary program operation is performed on memory cells to be programmed, such that a majority of the memory cells have a positive threshold voltage. An LSB of a particular memory cell is programmed to a predetermined level, and data of the programmed LSB is sensed. An MSB of the particular memory cell is programmed to a predetermined level according to the sensed data of the LSB.Type: ApplicationFiled: December 28, 2007Publication date: January 1, 2009Applicant: Hynix Semiconductor Inc.Inventor: Kyung Pil HWANG
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Publication number: 20090003072Abstract: A non-volatile memory device is provided. In an aspect, the non-volatile memory device includes two or more common source lines that are included in one memory cell block in order to distribute the current that could have been concentrated on one common source line. As a result, the bouncing phenomenon generated by the nose of the source line can be reduced. That is, at the time of a verifying operation performed during a program operation, the current concentrated on a common source line can be distributed and, therefore, the occurrence of under-programmed cells can be prevented.Type: ApplicationFiled: March 7, 2008Publication date: January 1, 2009Applicant: Hynix Semiconductor Inc.Inventors: Kyung Pil Hwang, Won Sic Woo
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Publication number: 20080230830Abstract: A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.Type: ApplicationFiled: March 21, 2008Publication date: September 25, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Se Jun KIM, Eun Seok CHOI, Kyoung Hwan PARK, Hyun Seung YOO, Myung Shik LEE, Young Ok HONG, Jung Ryul AHN, Yong Top KIM, Kyung Pil HWANG, Won Sic WOO, Jae Young PARK, Ki Hong LEE, Ki Seon PARK, Moon Sig JOO
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Patent number: 6660604Abstract: The present invention relates to a method of forming a dual junction region and a method of forming a transfer transistor using the same. A low-concentration junction region is formed. A high-concentration junction region is formed at a portion of the low-concentration junction region by performing a high-concentration ion implantation process an ion implantation mask for an interlayer dielectric film in which a contact hole is formed so that the portion of the low-concentration junction region is exposed. With this structure, the distance between the high-concentration junction region and the well is sufficiently secured by controlling the distance between the high-concentration junction region and the well using the width of the contact hole formed in the interlayer dielectric film. Therefore, a stable characteristic can be secured upon application of a subsequent high voltage bias.Type: GrantFiled: December 9, 2002Date of Patent: December 9, 2003Assignee: Hynix Semiconductor Inc.Inventors: Kyung Pil Hwang, Seoung Ouk Choi