Abstract: A fingerprint detecting apparatus includes a plurality of fingerprint sensor devices. Each of the plurality of fingerprint sensor devices includes a first conductive layer in which a sensing electrode configured to receive a response signal from a subject according to application of a driving voltage is formed, a shield layer formed under the first conductive layer, and to which a ground potential is applied, a second conductive layer formed under the shield layer, a third conductive layer formed in a part under the second conductive layer, a gain controller formed between the second conductive layer and the third conductive layer, and configured to selectively vary again, and an amplifier configured to generate an output signal formed by amplifying the response signal as much as the gain. The response signal and the output signal are received and output independently from an adjacent fingerprint sensor device.

Abstract: A fingerprint detection device including a sensor array including a plurality of fingerprint sensor elements arranged in a form of a matrix having a plurality of rows and columns, a filter and buffer unit including a plurality of first banks, each of which is configured to perform a noise elimination operation and a temporal storage operation in parallel with respect to output signals of some different columns of the sensor array. Each of the plurality of first banks simultaneously or consecutively acquires output signals from the fingerprint sensor elements belonging to columns spaced apart from each other by a predetermined distance. A sample and hold unit including second banks, the number of which being the same as the number of the plurality of first banks, performs a sampling and hold function in parallel in response to output signals from the plurality of first banks. An input/output unit receives an output signal from the sample and hold unit to output data of the sensor array.

Abstract: A fingerprint detection device including a sensor array including a plurality of fingerprint sensor elements arranged in a form of a matrix having a plurality of rows and columns, a filter and buffer unit including a plurality of first banks, each of which is configured to perform a noise elimination operation and a temporal storage operation in parallel with respect to output signals of some different columns of the sensor array. Each of the plurality of first banks simultaneously or consecutively acquires output signals from the fingerprint sensor elements belonging to columns spaced apart from each other by a predetermined distance. A sample and hold unit including second banks, the number of which being the same as the number of the plurality of first banks, performs a sampling and hold function in parallel in response to output signals from the plurality of first banks. An input/output unit receives an output signal from the sample and hold unit to output data of the sensor array.

Abstract: A memory device is provided that latches a plurality of data larger than a number of input or output bits and sequentially controls the transmission of the data for input/output preferably using a higher speed clock. The memory device can be a synchronous SRAM circuit that includes a control unit outputting a burst mode signal, an address decoder receiving an externally inputted address signal and the burst mode signal, outputting an internal address signal and a block coding signal, and a counter enabled by the burst mode signal and counting the block coding signal and outputting a coding signal. A multiplexer receives cell data from a plurality of sense amplifiers of the sense amplifier to concurrently latch the plurality of cell data having a prescribed number of bits larger than the number of external input and output bits and outputs one cell data among a plurality of the cell data in accordance with the coding signal. The latched data can be sequentially output to the outside using the counter.

Abstract: An output buffer circuit for a semiconductor device, capable of uniformly maintaining an output level regardless of an increase of a variable supply voltage VCC and improving an output speed, which includes a constant voltage generation circuit receiving the variable VCC and generating a constant voltage at a predetermined level, an inverter outputting data signals in accordance with the constant voltage outputted from the constant voltage generation circuit and first and second clock signals, a clock signal generation unit generating a third clock signal having a predetermined interval in accordance with the first clock signal and the data signals outputted from the inverter, and a pull-up transistor pulling up the output data signals of a high level at a predetermined level in accordance with the third clock signal.

Abstract: A data reading circuit for a semiconductor memory device is provided that reduces noise effects by stably operating a latch sense amplifier during a high speed operation. The data reading circuit produces a stable output voltage. The data reading circuit includes a sense amplifier controller that generates a first pulse signal having a time width for fully equalizing a sense amplifier. The sense amplifier generates the first pulse signal by delaying an address transition detection signal while a high level read signal is being outputted. The sense amplifier controller also combines the address transition detection signal and the first pulse signal to output a second pulse signal. A first current mode dual latch sense amplifier senses a data signal from a memory cell in accordance with the second pulse signal from the sense amplifier controller and transfers the sensed data in accordance with the first pulse signal.

Abstract: An input buffer circuit of a semiconductor memory device in which data is accessed by driving a decoder based on first and second internal address signals, the input buffer circuit including a first circuit for summing an input address and a chip selection signal to generate a first address signal, first and second inverters for inverting the first address signal and generating the first internal address signal and a second address signal, a detector circuit receiving the first internal address signal and the second address signal and detecting a HIGH of the first internal address signal and a LOW of the second address signal, and a second circuit for summing an output of the detection means and the second address signal and generating the second internal address signal.

Abstract: An input signal variation detection circuit effectively detects transitions of input signals from a memory apparatus. The circuit includes a plurality of unit blocks for detecting transitions of input signals and for outputting transition detection signals corresponding to the transition direction, e.g., from high to low level or from low to high level, a first transistor having a drain coupled for receiving a transition detection signal from the unit blocks, a gate coupled for receiving a first prescribed voltage, and a source coupled for receiving a second prescribed voltage, and an OR-gate for ORing a transition detection signal from the unit blocks and outputting a summation signal.

Abstract: An output buffer circuit of a semiconductor memory device, the circuit includes an address transition detector detecting a transition of address signals, a NOR gate coupled to the address transition detector and receiving signals from the address transition detector and on output enable signal and outputting a signal having a logical NOR result, a decoder decoding the address signals, a memory unit coupled to the decoder and outputting data from the decoder, a sensing amplifier coupled to the memory unit and amplifying data outputted from the memory unit, an output data controller coupled to the NOR gate and the sensing amplifier and controlling output signals from the NOR gate and the sensing amplifier, a data output unit coupled to the pull-up unit and the output data controller and outputting data in accordance with output signals from the output data controller, a preset unit coupled to the output data controller and presetting an output terminal of the data output unit during a pulse interval of an outpu

Abstract: An improved power supply control circuit capable of restricting operation of a peripheral circuit before the level of voltage is stabilized and permitting the peripheral circuit to operate after the level of voltage is stabilized, which includes a level detecting unit having a plurality of serially connected transistors for decreasing the level of voltage applied to one side thereof in order; and a disenable signal generating unit, which has MOS transistors having a different channel and connected between voltage and the ground, for receiving a different level of voltage from the level detecting unit and for generating a certain disenable signal when the voltage reaches a certain level.

Abstract: A metal oxide semiconductor transistor including a silicon substrate of a first conductivity type and having a central portion having a channel region which has a recessed surface. The substrate has another portion which has a flat surface. A thin gate oxide film is formed on the recessed surface and an oxide film, which is thicker than the gate oxide film, is formed on the flat surface. A gate is formed on the gate oxide film and has a flat upper surface and a convex lower surface. A thick cap oxide film is formed on the gate. Low concentration source and drain regions of a second conductivity type overlap completely with the gate and are formed adjacent to the channel region. High concentration source and drain regions of the second conductivity type are formed on the flat surface of the silicon substrate and adjacent to the low concentration source and drain regions.