Patents by Inventor KyungSeon HWANG

KyungSeon HWANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11869878
    Abstract: A semiconductor module includes a module substrate, a semiconductor package mounted on the module substrate, a first bonding wire connecting the module substrate to the semiconductor package, and a first molding member covering the first bonding wire. The semiconductor package includes a package substrate, a semiconductor chip mounted on the package substrate, a second bonding wire connecting the package substrate to the semiconductor chip, and a second molding member covering the semiconductor chip and the second bonding wire. The first and second bonding wires are each connected to one connection pad of the package substrate.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: January 9, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyungseon Hwang, Wonyoung Kim, Jinchan Ahn
  • Patent number: 11769746
    Abstract: A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate and electrically connected to the through-electrodes, respectively, and at least one second bump disposed between the first bumps and electrically insulated from the through-electrodes. The first bumps and the at least one second bump constitute one row in the first direction. A level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: September 26, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ae-Nee Jang, KyungSeon Hwang, SunWon Kang
  • Publication number: 20220059506
    Abstract: A semiconductor module includes a module substrate, a semiconductor package mounted on the module substrate, a first bonding wire connecting the module substrate to the semiconductor package, and a first molding member covering the first bonding wire. The semiconductor package includes a package substrate, a semiconductor chip mounted on the package substrate, a second bonding wire connecting the package substrate to the semiconductor chip, and a second molding member covering the semiconductor chip and the second bonding wire. The first and second bonding wires are each connected to one connection pad of the package substrate.
    Type: Application
    Filed: November 5, 2021
    Publication date: February 24, 2022
    Inventors: KYUNGSEON HWANG, WONYOUNG KIM, JINCHAN AHN
  • Patent number: 11171119
    Abstract: A semiconductor module includes a module substrate, a semiconductor package mounted on the module substrate, a first bonding wire connecting the module substrate to the semiconductor package, and a first molding member covering the first bonding wire. The semiconductor package includes a package substrate, a semiconductor chip mounted on the package substrate, a second bonding wire connecting the package substrate to the semiconductor chip, and a second molding member covering the semiconductor chip and the second bonding wire. The first and second bonding wires are each connected to one connection pad of the package substrate.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: November 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyungseon Hwang, Wonyoung Kim, Jinchan Ahn
  • Publication number: 20210183801
    Abstract: A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate and electrically connected to the through-electrodes, respectively, and at least one second bump disposed between the first bumps and electrically insulated from the through-electrodes. The first bumps and the at least one second bump constitute one row in the first direction. A level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate.
    Type: Application
    Filed: March 2, 2021
    Publication date: June 17, 2021
    Inventors: Ae-nee JANG, KyungSeon HWANG, SunWon KANG
  • Patent number: 10943881
    Abstract: A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate and electrically connected to the through-electrodes, respectively, and at least one second bump disposed between the first bumps and electrically insulated from the through-electrodes. The first bumps and the at least one second bump constitute one row in the first direction. A level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: March 9, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ae-nee Jang, KyungSeon Hwang, SunWon Kang
  • Publication number: 20200365559
    Abstract: A semiconductor module includes a module substrate, a semiconductor package mounted on the module substrate, a first bonding wire connecting the module substrate to the semiconductor package, and a first molding member covering the first bonding wire. The semiconductor package includes a package substrate, a semiconductor chip mounted on the package substrate, a second bonding wire connecting the package substrate to the semiconductor chip, and a second molding member covering the semiconductor chip and the second bonding wire. The first and second bonding wires are each connected to one connection pad of the package substrate.
    Type: Application
    Filed: November 26, 2019
    Publication date: November 19, 2020
    Inventors: KYUNGSEON HWANG, WONYOUNG KIM, JINCHAN AHN
  • Publication number: 20190164922
    Abstract: A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate and electrically connected to the through-electrodes, respectively, and at least one second bump disposed between the first bumps and electrically insulated from the through-electrodes. The first bumps and the at least one second bump constitute one row in the first direction. A level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate.
    Type: Application
    Filed: January 10, 2019
    Publication date: May 30, 2019
    Inventors: Ae-nee JANG, KyungSeon HWANG, SunWon KANG
  • Patent number: 10211176
    Abstract: A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate and electrically connected to the through-electrodes, respectively, and at least one second bump disposed between the first bumps and electrically insulated from the through-electrodes. The first bumps and the at least one second bump constitute one row in the first direction. A level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: February 19, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ae-nee Jang, KyungSeon Hwang, SunWon Kang
  • Publication number: 20170179062
    Abstract: A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate and electrically connected to the through-electrodes, respectively, and at least one second bump disposed between the first bumps and electrically insulated from the through-electrodes. The first bumps and the at least one second bump constitute one row in the first direction. A level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate.
    Type: Application
    Filed: December 12, 2016
    Publication date: June 22, 2017
    Inventors: Ae-nee JANG, KyungSeon HWANG, SunWon KANG