Patents by Inventor Kyung-Soo Ha

Kyung-Soo Ha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220383931
    Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.
    Type: Application
    Filed: July 29, 2022
    Publication date: December 1, 2022
    Inventors: DAE-SIK MOON, GIL-HOON CHA, KI-SEOK OH, CHANG-KYO LEE, YEON-KYU CHOI, JUNG-HWAN CHOI, KYUNG-SOO HA, SEOK-HUN HYUN
  • Patent number: 11508420
    Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: November 22, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Donghun Lee, Daesik Moon, Young-Soo Sohn, Young-Hoon Son, Ki-Seok Oh, Changkyo Lee, Hyun-Yoon Cho, Kyung-Soo Ha, Seokhun Hyun
  • Patent number: 11475930
    Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: October 18, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Hoon Son, Si-Hong Kim, Chang-Kyo Lee, Jung-Hwan Choi, Kyung-Soo Ha
  • Publication number: 20220310151
    Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.
    Type: Application
    Filed: June 16, 2022
    Publication date: September 29, 2022
    Inventors: Dae-Sik MOON, Gil-Hoon CHA, Ki-Seonk OH, Chang-Kyo LEE, Yeon-Kyu CHOI, Jung-Hwan CHOI, Kyung-Soo HA, Seok-Hun HYUN
  • Patent number: 11423971
    Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: August 23, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae-Sik Moon, Gil-Hoon Cha, Ki-Seok Oh, Chang-Kyo Lee, Yeon-Kyu Choi, Jung-Hwan Choi, Kyung-Soo Ha, Seok-Hun Hyun
  • Patent number: 11393340
    Abstract: An automatic parking system includes a sensor detecting parking areas depending on a size of a subject vehicle and a controller controlling the subject vehicle to be parked in an optimal parking area among the parking areas, in which the sensor may detect the parking areas in consideration of a length and a width of the subject vehicle and detect a spaced distance from surrounding vehicles positioned on a side of the subject vehicle in the optimal parking area and the controller may calculate a moving path between a current position of the subject vehicle and the optimal parking area and compare a predetermined reference distance and the spaced distances to control the subject vehicle.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: July 19, 2022
    Assignees: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATION
    Inventors: Yoon Soo Kim, Jin Ho Park, Joo Woong Yang, Jae Hwan Jeon, Kyung Soo Ha, Min Byeong Lee, Seung Wook Park, Jong Ho Lee, In Yong Jung
  • Patent number: 11393522
    Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: July 19, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae-Sik Moon, Gil-Hoon Cha, Ki-Seok Oh, Chang-Kyo Lee, Yeon-Kyu Choi, Jung-Hwan Choi, Kyung-Soo Ha, Seok-Hun Hyun
  • Patent number: 11327838
    Abstract: A memory device includes: a first memory bank and a second memory bank; a control logic configured to receive a command and control an internal operation of the memory device; and an error correction code (ECC) circuit configured to retain in a latch circuit first read data read from the first memory bank in response to a first masked write (MWR) command for the first memory bank based on a latch control signal from the control logic, generate a first parity from data in which the first read data retained in the latch circuit is merged with first write data corresponding to the first MWR command in response to a first write control signal received from the control logic, and control an ECC operation to retain in the latch circuit second read data read from the second memory bank based on the latch control signal.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: May 10, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Hwan Park, Tae-Young Oh, Hyung-Joon Chi, Kyung-Soo Ha, Hyong-Ryol Hwang
  • Publication number: 20220122648
    Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.
    Type: Application
    Filed: December 29, 2021
    Publication date: April 21, 2022
    Inventors: DAE-SIK MOON, GIL-HOON CHA, KI-SEOK OH, CHANG-KYO LEE, YEON-KYU CHOI, JUNG-HWAN CHOI, KYUNG-SOO HA, SEOK-HUN HYUN
  • Patent number: 11305755
    Abstract: An apparatus for remotely controlling an exit mode in a vehicle includes a driver detector that detects a location of a driver, an obstacle detector that detects an obstacle located around the vehicle, and a controller that sets an exit mode of a remotely started vehicle based on the location of the driver, detected by the driver detector, and the location of the obstacle, detected by the obstacle detector.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: April 19, 2022
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventors: Jong Ho Park, Kyung Soo Ha, Gil Won Seo
  • Publication number: 20220093200
    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register, a scrubbing control circuit and a control logic circuit. The memory cell array includes memory cell rows. The scrubbing control circuit generates scrubbing addresses based on refresh operations performed on the memory cell array. The control logic circuit controls the ECC circuit such that the ECC circuit performs an error detection operation on a plurality of sub-pages in a first memory cell row to count a number of error occurrences, and determines whether to correct a codeword in which an error is detected based on the number of error occurrences. An uncorrected or corrected codeword is written back , and a row address of the first memory cell row may be stored in the fault address register as a row fault address based on the number of error occurrences.
    Type: Application
    Filed: April 30, 2021
    Publication date: March 24, 2022
    Inventors: Kiheung Kim, Sanguhn Cha, Junhyung Kim, Sungchul Park, Hyojin Jung, Kyung-Soo Ha
  • Publication number: 20220093144
    Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.
    Type: Application
    Filed: December 1, 2021
    Publication date: March 24, 2022
    Inventors: DAE-SIK MOON, KYUNG-SOO HA, YOUNG-SOO SOHN, KI-SEOK OH, CHANG-KYO LEE, JIN-HOON JANG, YEON-KYU CHOI, SEOK-HUN HYUN
  • Publication number: 20220059148
    Abstract: There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.
    Type: Application
    Filed: November 4, 2021
    Publication date: February 24, 2022
    Inventors: Young-hun KIM, Si-hong KIM, Tae-young OH, Kyung-soo HA
  • Patent number: 11211102
    Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: December 28, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae-Sik Moon, Kyung-Soo Ha, Young-Soo Sohn, Ki-Seok Oh, Chang-Kyo Lee, Jin-Hoon Jang, Yeon-Kyu Choi, Seok-Hun Hyun
  • Patent number: 11195566
    Abstract: There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: December 7, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-hun Kim, Si-hong Kim, Tae-young Oh, Kyung-soo Ha
  • Patent number: 11155299
    Abstract: An automatic parking system includes a sensor system measuring whether there is a parking section line and positions of surrounding vehicles, and a controller configured to analyze data sensed by the sensor system to calculate parking areas around a subject vehicle, calculate a range allowing generation of a moving path based on the parking areas, provide a moving path range for a parking type that is selected among the moving path ranges provided for the at least two parking types, and an optimal parking area for the selected moving path range, and automatically park the subject vehicle in the optimal parking area.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: October 26, 2021
    Assignees: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATION
    Inventors: Yoon Soo Kim, Joo Woong Yang, Dae Joong Yoon, Eu Gene Chang, Jae Seob Choi, Kyung Soo Ha, Min Byeong Lee, Seung Wook Park, Jin Ho Park, In Yong Jung
  • Publication number: 20210327476
    Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.
    Type: Application
    Filed: June 23, 2021
    Publication date: October 21, 2021
    Inventors: DONGHUN LEE, Daesik MOON, Young-Soo SOHN, Young-Hoon SON, Ki-Seok OH, Changkyo LEE, Hyun-Yoon CHO, Kyung-Soo HA, Seokhun HYUN
  • Patent number: 11124181
    Abstract: A vehicle control device includes a processor configured to determine a danger of collision between a user located within a specific distance from a first vehicle and a second vehicle that is traveling, warn the danger of collision through the first vehicle or a user terminal of the user according to the danger of collision, or control movement of the first vehicle, or transmit warning information to the second vehicle, and a storage configured to store information calculated by the processor.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: September 21, 2021
    Assignees: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATION
    Inventors: Dae Joong Yoon, Kyung Soo Ha, Sun Wo Jung, Jin Ho Park, Wan Seok Yang
  • Publication number: 20210233575
    Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.
    Type: Application
    Filed: January 5, 2021
    Publication date: July 29, 2021
    Inventors: YOUNG-HOON SON, SI-HONG KIM, CHANG-KYO LEE, JUNG-HWAN CHOI, KYUNG-SOO HA
  • Patent number: 11062744
    Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: July 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Donghun Lee, Daesik Moon, Young-Soo Sohn, Young-Hoon Son, Ki-Seok Oh, Changkyo Lee, Hyun-Yoon Cho, Kyung-Soo Ha, Seokhun Hyun