Abstract: A parity error detecting circuit includes a first operation unit, a second operation unit, and a shift register. The first operation unit receives a serial data signal and a first signal, performs a logic operation on the two received signals, and outputs the result of the logic operation as the first signal in response to a first clock signal. The shift register shifts the first signal in response to the first clock signal and outputs a second signal. The second operation unit receives the first signal and the second signal, performs a logic operation on the two received signals, and outputs the result of the logic operation in response to a second clock signal.

Abstract: A parity error detecting circuit includes a first operation unit, a second operation unit, and a shift register. The first operation unit receives a serial data signal and a first signal, performs a logic operation on the two received signals, and outputs the result of the logic operation as the first signal in response to a first clock signal. The shift register shifts the first signal in response to the first clock signal and outputs a second signal. The second operation unit receives the first signal and the second signal, performs a logic operation on the two received signals, and outputs the result of the logic operation in response to a second clock signal.

Abstract: Provided is a circuit for compensating for the declination of balanced impedance elements and a frequency mixer. The compensation circuit compensates for a difference between impedance measured at first and second impedance elements, and comprises first and second impedance circuits. The first impedance circuit transforms a first impedance value into a fine impedance value having 2n steps in response to n lower bits of a control signal having k bits. The second impedance circuit transforms a second impedance value into a coarse impedance value having 2m steps in response to m upper bits of the control signal. The first and second impedance values are measured at the first and second impedance elements, respectively, and k is equal to m plus n. The impedance difference between the impedance elements is linearly regulated.

Abstract: A low voltage differential signal (LVDS) receiver includes a first receiving unit configured to receive a reference voltage and to responsively generate a first differential signal, and a second receiving unit configured to receive a voltage developed across a variable termination resistor unit having a resistance that is adjustable based on a resistance control code in response to a reference current, and to responsively generate a second differential signal. The LVDS receiver further includes a comparing unit configured to compare the first differential signal with the second differential signal and to responsively generate a counter control signal. The LVDS receiver further includes an up/down counter configured to adjust the resistance control code in response to the counter control signal. The up/down counter is further configured to provide the resistance control code to the variable termination resistor unit. Corresponding methods are also disclosed.

Abstract: A low voltage differential signal (LVDS) receiver includes a first receiving unit configured to receive a reference voltage and to responsively generate a first differential signal, and a second receiving unit configured to receive a voltage developed across a variable termination resistor unit having a resistance that is adjustable based on a resistance control code in response to a reference current, and to responsively generate a second differential signal. The LVDS receiver further includes a comparing unit configured to compare the first differential signal with the second differential signal and to responsively generate a counter control signal. The LVDS receiver further includes an up/down counter configured to adjust the resistance control code in response to the counter control signal. The up/down counter is further configured to provide the resistance control code to the variable termination resistor unit. Corresponding methods are also disclosed.

Abstract: Provided is a circuit for compensating for the declination of balanced impedance elements and a frequency mixer. The compensation circuit compensates for a difference between impedance measured at first and second impedance elements, and comprises first and second impedance circuits. The first impedance circuit transforms a first impedance value into a fine impedance value having 2n steps in response to n lower bits of a control signal having k bits. The second impedance circuit transforms a second impedance value into a coarse impedance value having 2m steps in response to m upper bits of the control signal. The first and second impedance values are measured at the first and second impedance elements, respectively, and k is equal to m plus n. The impedance difference between the impedance elements is linearly regulated.

Abstract: Provided is a circuit for compensating for the declination of balanced impedance elements and a frequency mixer. The compensation circuit compensates for a difference between impedance measured at first and second impedance elements, and comprises first and second impedance circuits. The first impedance circuit transforms a first impedance value into a fine impedance value having 2n steps in response to n lower bits of a control signal having k bits. The second impedance circuit transforms a second impedance value into a coarse impedance value having 2m steps in response to m upper bits of the control signal. The first and second impedance values are measured at the first and second impedance elements, respectively, and k is equal to m plus n. The impedance difference between the impedance elements is linearly regulated.

Abstract: Provided is a circuit for compensating for the declination of balanced impedance elements and a frequency mixer. The compensation circuit compensates for a difference between impedance measured at first and second impedance elements, and comprises first and second impedance circuits. The first impedance circuit transforms a first impedance value into a fine impedance value having 2n steps in response to n lower bits of a control signal having k bits. The second impedance circuit transforms a second impedance value into a coarse impedance value having 2m steps in response to m upper bits of the control signal. The first and second impedance values are measured at the first and second impedance elements, respectively, and k is equal to m plus n. The impedance difference between the impedance elements is linearly regulated.

Abstract: A phase lock detection circuit includes a phase detection circuit that produces a phase detect signal having one of a first logic state or a second logic state responsive to a first input signal and a second input signal applied thereto. A stabilized phase lock indication circuit is electrically coupled to the phase detection circuit and produces a phase lock indication signal having one of a first logic state or a second logic state, the phase lock indication signal changing to a respective one of its first and second logic states in response to the phase detect signal remaining in a respective one of its first and second logic states for a predetermined time interval. In a first embodiment, the phase lock indication is controlled by monitoring a digital count. In a second embodiment, the phase lock indication signal is controlled by monitoring a capacitor voltage. Related operating methods are also discussed.

Abstract: A phase lock detection circuit includes a phase detection circuit that produces a phase detect signal having one of a first logic state or a second logic state responsive to a first input signal and a second input signal applied thereto. A stabilized phase lock indication circuit is electrically coupled to the phase detection circuit and produces a phase lock indication signal having one of a first logic state or a second logic state, the phase lock indication signal changing to a respective one of its first and second logic states in response to the phase detect signal remaining in a respective one of its first and second logic states for a predetermined time interval. In a first embodiment, the phase lock indication is controlled by monitoring a digital count. In a second embodiment, the phase lock indication signal is controlled by monitoring a capacitor voltage. Related operating methods are also discussed.