Patents by Inventor Kyung-tae Jang

Kyung-tae Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250034083
    Abstract: The present invention relates to novel functional derivatives of alanine and proline amino acids. The compounds of the present invention were confirmed to have a very superior antifungal or fungicidal effect. In addition, the compounds of the present invention were confirmed to exhibit a synergistic effect when co-administered with an existing antifungal preparation. Moreover, the compounds of the present invention showed activity on a wide range of fungi. Therefore, the compounds of the present invention can be widely used in a field which requires the treatment with an antifungal or fungicidal preparation against human infectious fungi, animal infectious fungi, and phytopathogenic fungi.
    Type: Application
    Filed: October 17, 2024
    Publication date: January 30, 2025
    Inventors: Ki Duk PARK, Yong-Sun BAHN, Jong-Seung LEE, Kyung-Tae LEE, Ae Nim PAE, Seul Ki YEON, Yong Koo KANG, Jong Hyun PARK, Siwon KIM, Bo Ko JANG, Ji Won CHOI
  • Publication number: 20250034082
    Abstract: The present invention relates to novel functional derivatives of alanine and proline amino acids. The compounds of the present invention were confirmed to have a very superior antifungal or fungicidal effect. In addition, the compounds of the present invention were confirmed to exhibit a synergistic effect when co-administered with an existing antifungal preparation. Moreover, the compounds of the present invention showed activity on a wide range of fungi. Therefore, the compounds of the present invention can be widely used in a field which requires the treatment with an antifungal or fungicidal preparation against human infectious fungi, animal infectious fungi, and phytopathogenic fungi.
    Type: Application
    Filed: October 17, 2024
    Publication date: January 30, 2025
    Inventors: Ki Duk PARK, Yong-Sun BAHN, Jong-Seung LEE, Kyung-Tae LEE, Ae Nim PAE, Seul Ki YEON, Yong Koo KANG, Jong Hyun PARK, Siwon KIM, Bo Ko JANG, Ji Won CHOI
  • Publication number: 20250034084
    Abstract: The present invention relates to novel functional derivatives of alanine and proline amino acids. The compounds of the present invention were confirmed to have a very superior antifungal or fungicidal effect. In addition, the compounds of the present invention were confirmed to exhibit a synergistic effect when co-administered with an existing antifungal preparation. Moreover, the compounds of the present invention showed activity on a wide range of fungi. Therefore, the compounds of the present invention can be widely used in a field which requires the treatment with an antifungal or fungicidal preparation against human infectious fungi, animal infectious fungi, and phytopathogenic fungi.
    Type: Application
    Filed: October 17, 2024
    Publication date: January 30, 2025
    Inventors: Ki Duk PARK, Yong-Sun BAHN, Jong-Seung LEE, Kyung-Tae LEE, Ae Nim PAE, Seul Ki YEON, Yong Koo KANG, Jong Hyun PARK, Siwon KIM, Bo Ko JANG, Ji Won CHOI
  • Publication number: 20250034085
    Abstract: The present invention relates to novel functional derivatives of alanine and proline amino acids. The compounds of the present invention were confirmed to have a very superior antifungal or fungicidal effect. In addition, the compounds of the present invention were confirmed to exhibit a synergistic effect when co-administered with an existing antifungal preparation. Moreover, the compounds of the present invention showed activity on a wide range of fungi. Therefore, the compounds of the present invention can be widely used in a field which requires the treatment with an antifungal or fungicidal preparation against human infectious fungi, animal infectious fungi, and phytopathogenic fungi.
    Type: Application
    Filed: October 17, 2024
    Publication date: January 30, 2025
    Inventors: Ki Duk PARK, Yong-Sun BAHN, Jong-Seung LEE, Kyung-Tae LEE, Ae Nim PAE, Seul Ki YEON, Yong Koo KANG, Jong Hyun PARK, Siwon KIM, Bo Ko JANG, Ji Won CHOI
  • Patent number: 9780113
    Abstract: A method for fabricating a semiconductor device includes forming a stacked structure on a substrate, forming a first interlayer dielectric covering the stacked structure, and forming a second interlayer dielectric covering the first interlayer dielectric. The stacked structure includes a stepwise shape. The first interlayer dielectric includes at least one step portion having a slope surface connecting a first top surface to a second top surface. The first top surface and the sloped surface define a first angle that is an obtuse angle. A level of the second top surface is higher than a level of the first top surface.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: October 3, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jiwoon Im, Kwangchul Park, Jiyoun Seo, Jongmyeong Lee, Kyung-Tae Jang, Byungho Chun, Won-Seok Jung, Jongwan Choi, Tae-Jong Han
  • Publication number: 20160233232
    Abstract: A method for fabricating a semiconductor device includes forming a stacked structure on a substrate, forming a first interlayer dielectric covering the stacked structure, and forming a second interlayer dielectric covering the first interlayer dielectric. The stacked structure includes a stepwise shape. The first interlayer dielectric includes at least one step portion having a slope surface connecting a first top surface to a second top surface. The first top surface and the sloped surface define a first angle that is an obtuse angle. A level of the second top surface is higher than a level of the first top surface.
    Type: Application
    Filed: December 9, 2015
    Publication date: August 11, 2016
    Inventors: Jiwoon IM, Kwangchul PARK, Jiyoun SEO, Jongmyeong LEE, Kyung-Tae JANG, Byungho CHUN, Won-Seok JUNG, Jongwan CHOI, Tae-Jong HAN
  • Patent number: 9343475
    Abstract: In a method of a vertical memory device, insulation layers and sacrificial layers are alternately and repeatedly formed on a substrate. A hole is formed through the insulation layers and the sacrificial layers that expose a top surface of the substrate. Then, an interior portion of the hole may be enlarged. A semiconductor pattern is formed to partially fill the enlarged portion of the hole. A blocking layer, a charge storage layer and a tunnel insulation layer may be formed on a sidewall of the hole and the semiconductor pattern. Then, the tunnel insulation layer, the charge storage layer and the blocking layer are partially removed to expose a top surface of the semiconductor pattern. A channel is formed on the exposed top surface of the semiconductor pattern and the tunnel insulation layer. The sacrificial layers are replaced with gate electrodes.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: May 17, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Tae Jang, Sang-Hoon Lee, Ji-Youn Seo, Hyun-Yong Go, Koong-Hyun Nam, Ju-Wan Kim, Seung-Mok Shin, Myoung-Bum Lee, Ji-Woon Im, Tae-Jong Han
  • Patent number: 9312270
    Abstract: Methods of manufacturing a three-dimensional semiconductor device are provided. The method includes: forming a thin film structure, where first and second material layers of at least 2n (n is an integer more than 2) are alternately and repeatedly stacked, on a substrate; wherein the first material layer applies a stress in a range of about 0.1×109 dyne/cm2 to about 10×109 dyne/cm2 to the substrate and the second material layer applies a stress in a range of about ?0.1×109 dyne/cm2 to about ?10×109 dyne/cm2 to the substrate.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: April 12, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Tae Jang, Myoungbum Lee, Seungmok Shin, JinGyun Kim, Yeon-Sil Sohn, Seung-Yup Lee, Dae-Hun Choi
  • Patent number: 9184178
    Abstract: A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: November 10, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung-Tae Jang, Myoung-Bum Lee, Ji-Youn Seo, Chang-Won Lee, Yong-Chae Jung, Woong-Hee Sohn
  • Publication number: 20150200203
    Abstract: In a method of a vertical memory device, insulation layers and sacrificial layers are alternately and repeatedly formed on a substrate. A hole is formed through the insulation layers and the sacrificial layers that expose a top surface of the substrate. Then, an interior portion of the hole may be enlarged. A semiconductor pattern is formed to partially fill the enlarged portion of the hole. A blocking layer, a charge storage layer and a tunnel insulation layer may be formed on a sidewall of the hole and the semiconductor pattern. Then, the tunnel insulation layer, the charge storage layer and the blocking layer are partially removed to expose a top surface of the semiconductor pattern. A channel is formed on the exposed top surface of the semiconductor pattern and the tunnel insulation layer. The sacrificial layers are replaced with gate electrodes.
    Type: Application
    Filed: January 15, 2014
    Publication date: July 16, 2015
    Inventors: Kyung-Tae Jang, Sang-Hoon Lee, Ji-Youn Seo, Hyun-Yong Go, Koong-Hyun Nam, Ju-Wan Kim, Seung-Mok Shin, Myoung-Bum Lee, Ji-Woon Im, Tae-Jong Han
  • Publication number: 20150126007
    Abstract: Methods of manufacturing a three-dimensional semiconductor device are provided. The method includes: forming a thin film structure, where first and second material layers of at least 2n (n is an integer more than 2) are alternately and repeatedly stacked, on a substrate; wherein the first material layer applies a stress in a range of about 0.1×109 dyne/cm2 to about 10×109 dyne/cm2 to the substrate and the second material layer applies a stress in a range of about ?0.1×109 dyne/cm2 to about ?10×109 dyne/cm2 to the substrate.
    Type: Application
    Filed: January 9, 2015
    Publication date: May 7, 2015
    Inventors: Kyung-Tae Jang, Myoungbum Lee, Seungmok Shin, JinGyun Kim, Yeon-Sil Sohn, Seung-Yup Lee, Dae-Hun Choi
  • Publication number: 20150091078
    Abstract: A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.
    Type: Application
    Filed: December 9, 2014
    Publication date: April 2, 2015
    Inventors: Kyung-Tae Jang, Myoung-Bum Lee, Ji-Youn Seo, Chang-Won Lee, Yong-Chae Jung, Woong-Hee Sohn
  • Patent number: 8916922
    Abstract: A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: December 23, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Tae Jang, Myoung-Bum Lee, Ji-Youn Seo, Chang-Won Lee, Yong-Chae Jung, Woong-Hee Sohn
  • Patent number: 8691682
    Abstract: Methods of forming a semiconductor device include forming an insulation layer on a semiconductor structure, forming an opening in the insulation layer, the opening having a sidewall defined by one side of the insulation layer, forming a first metal layer in the opening, at least partially exposing the sidewall of the opening by performing a wet-etching process on the first metal layer, and selectively forming a second metal layer on the etched first metal layer. An average grain size of the first metal layer is smaller than an average grain size of the second metal layer. Related semiconductor devices are also disclosed.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: April 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tai-Soo Lim, HyunSeok Lim, Shin-Jae Kang, Kyung-Tae Jang
  • Publication number: 20140070300
    Abstract: A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.
    Type: Application
    Filed: December 21, 2012
    Publication date: March 13, 2014
    Inventors: Kyung-Tae Jang, Myoung-Bum Lee, Ji-Youn Seo, Chang-Won Lee, Yong-Chae Jung, Woong-Hee Sohn
  • Patent number: 8643084
    Abstract: A vertical non-volatile memory device includes a semiconductor pattern disposed on a substrate; and a plurality of transistors of first through n-th layers that are stacked on a side of the semiconductor pattern at predetermined distances from each other, wherein the transistors are spaced apart and insulated from one another at the predetermined distances via air gap, where n is a natural number equal to or greater than 2.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: February 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Mok Shin, Kyung-Tae Jang, Chang-Won Lee
  • Patent number: 8440531
    Abstract: Methods of forming vertical nonvolatile memory devices utilize carbon-blocking sacrificial capping layers to increase device yield by reducing the likelihood that one or more vertically-stacked layers of materials will lift-off during fabrication. These capping layers may be provided to cover carbon-containing sacrificial layers that are highly polymerized.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: May 14, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Jong Han, Daewoong Kim, Kyung-Tae Jang, Bongcheol Kim, Ohchel Kwon
  • Patent number: 8415674
    Abstract: Methods of forming a semiconductor device include forming an insulation layer on a semiconductor structure, forming an opening in the insulation layer, the opening having a sidewall defined by one side of the insulation layer, forming a first metal layer in the opening, at least partially exposing the sidewall of the opening by performing a wet-etching process on the first metal layer, and selectively forming a second metal layer on the etched first metal layer. An average grain size of the first metal layer is smaller than an average grain size of the second metal layer. Related semiconductor devices are also disclosed.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: April 9, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tai-Soo Lim, HyunSeok Lim, Shin-Jae Kang, Kyung-Tae Jang
  • Publication number: 20120276719
    Abstract: Methods of forming vertical nonvolatile memory devices utilize carbon-blocking sacrificial capping layers to increase device yield by reducing the likelihood that one or more vertically-stacked layers of materials will lift-off during fabrication. These capping layers may be provided to cover carbon-containing sacrificial layers that are highly polymerized.
    Type: Application
    Filed: April 17, 2012
    Publication date: November 1, 2012
    Inventors: Tae-Jong Han, Daewoong Kim, Kyung-Tae Jang, Bongcheol Kim, Ohchel Kwon
  • Publication number: 20120064682
    Abstract: Methods of manufacturing a three-dimensional semiconductor device are provided. The method includes: forming a thin film structure, where first and second material layers of at least 2n (n is an integer more than 2) are alternately and repeatedly stacked, on a substrate; wherein the first material layer applies a stress in a range of about 0.1×109 dyne/cm2 to about 10×109 dyne/cm2 to the substrate and the second material layer applies a stress in a range of about ?0.1×109 dyne/cm2 to about ?10×109 dyne/cm2 to the substrate.
    Type: Application
    Filed: September 12, 2011
    Publication date: March 15, 2012
    Inventors: Kyung-Tae Jang, Myoung Lee, Seungmok Shin, JinGyun Kim, Yeon-Sil Sohn, Seung-Yuo Lee, Dae-Hun Choi