Patents by Inventor Kyung-tae NA

Kyung-tae NA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240323569
    Abstract: An image sensor includes a pixel having first and second photodiodes, a storage capacitor, an overflow transistor, and a read circuit.
    Type: Application
    Filed: October 26, 2023
    Publication date: September 26, 2024
    Inventors: Ho Yong NA, Kyung-Min KIM, Young Tae JANG
  • Patent number: 9245863
    Abstract: According to example embodiments of inventive concepts, a semiconductor package apparatus includes a first semiconductor package including a first substrate, a first solder resist layer on the first substrate, and a first sealing member that covers and protects the first solder resist layer, and a plurality of solder balls on the first substrate. The plurality of solder balls includes a first solder ball having a first height and a second solder ball having a second height that is different from the first height. The first sealing member includes holes that expose the solder balls.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: January 26, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hae-jung Yu, Hak-kyoon Byun, Kyung-tae Na, Seung-hun Han, Tae-sung Park, Choong-bin Yim
  • Patent number: 8970042
    Abstract: A circuit board is provided including a core insulation film having a thickness and including a first surface and an opposite second surface, an upper stack structure and a lower stack structure. The upper stack structure has a thickness and has an upper conductive pattern having a thickness and an overlying upper insulation film stacked on the first surface of the core insulation film. The lower stack structure has a thickness and has a lower conductive pattern having a thickness and an overlying lower insulation film stacked on the second surface of the core insulation film. A ratio P of a sum of the thicknesses of the upper conductive pattern and the lower conductive pattern to a sum of the thicknesses of the core insulation film, the upper stack structure and the lower stack structure is in a range from about 0.05 to about 0.2.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bok-Sik Myung, Chul-Woo Kim, Kyung-Tae Na, Young-Bae Kim, Yong-Hoon Kim, Hee-Seok Lee
  • Publication number: 20150022985
    Abstract: A package substrate includes a core layer having a core top surface and a core bottom surface, and a build-up layer having a stacked structure in which a plurality of interconnection layers and a plurality of insulating layers are alternately stacked on the core top surface. The core bottom surface includes a board connecting area. A surface of the build-up layer includes a chip mounting area. The core layer includes at least one cavity defined by recess sidewalls extending upward from the core bottom surface and a recessed surface located at a higher level than or the same level as the core top surface, at least one device mounted in the at least one cavity, and through-electrodes electrically connecting the core top surface and the core bottom surface.
    Type: Application
    Filed: July 15, 2014
    Publication date: January 22, 2015
    Inventors: KYUNG-TAE NA, CHUL-WOO KIM, BOK-SIK MYUNG, SEUNG-HWAN LEE
  • Publication number: 20140091463
    Abstract: According to example embodiments of inventive concepts, a semiconductor package apparatus includes a first semiconductor package including a first substrate, a first solder resist layer on the first substrate, and a first sealing member that covers and protects the first solder resist layer, and a plurality of solder balls on the first substrate. The plurality of solder balls includes a first solder ball having a first height and a second solder ball having a second height that is different from the first height. The first sealing member includes holes that expose the solder balls.
    Type: Application
    Filed: July 16, 2013
    Publication date: April 3, 2014
    Inventors: Hae-jung YU, Hak-kyoon BYUN, Kyung-tae NA, Seung-hun HAN, Tae-sung PARK, Choong-bin YIM