Abstract: A multi-prober chuck assembly and channel are provided. The multi-prober chuck assembly, according to one embodiment of the present invention, comprises: a chuck for supporting a wafer; a probe card structure coupled to the top part of the chuck; a heater for heating the chuck under the chuck; a conductive guard plate spaced apart from the heater below the heater; and a body part positioned under the chuck so that the heater and the guard plate are positioned inside the body part, wherein the probe card structure and the body part are coupled mechanically to form a cartridge-type structure.

Abstract: A multi-prober chuck assembly and channel are provided. The multi-prober chuck assembly, according to one embodiment of the present invention, comprises: a chuck for supporting a wafer; a probe card structure coupled to the top part of the chuck; a heater for heating the chuck under the chuck; a conductive guard plate spaced apart from the heater below the heater; and a body part positioned under the chuck so that the heater and the guard plate are positioned inside the body part, wherein the probe card structure and the body part are coupled mechanically to form a cartridge-type structure.

Abstract: The present invention relates to a substrate testing cartridge provided for simultaneously testing multiple substrates for which a substrate treatment process has been finished, and a method for manufacturing same. According to an embodiment of the present invention, a substrate testing cartridge comprises: a chuck member on which a substrate is placed; a probe card which contacts and tests the substrate and is positioned to face the chuck member with reference to the substrate; and coupling members which couple the substrate, the chuck member, and the probe card, wherein each coupling member comprises: a substrate coupling part which couples the substrate and the chuck member; and a chuck coupling part which couples the probe card and the chuck member.

Abstract: The present invention relates to a substrate testing cartridge provided for simultaneously testing multiple substrates for which a substrate treatment process has been finished, and a method for manufacturing same. According to an embodiment of the present invention, a substrate testing cartridge comprises: a chuck member on which a substrate is placed; a probe card which contacts and tests the substrate and is positioned to face the chuck member with reference to the substrate; and coupling members which couple the substrate, the chuck member, and the probe card, wherein each coupling member comprises: a substrate coupling part which couples the substrate and the chuck member; and a chuck coupling part which couples the probe card and the chuck member.

Abstract: A semiconductor device includes a lower insulating layer on a substrate, a lower wiring layer extending on the lower insulating layer, a lower surface of at least a part of the lower wiring layer being covered by the lower insulating layer, a plurality of via plugs extending in a first direction on the lower wiring layer, the plurality of via plugs including a real via plug and a first dummy via plug connected to the part of the lower wiring layer covered by the lower insulating layer, and an upper wiring layer overlapping the lower wiring layer and extending in a second direction different from the first direction on the real via plug, the upper wiring layer not overlapping the dummy via plug.

Abstract: A semiconductor device includes a lower insulating layer on a substrate, a lower wiring layer extending on the lower insulating layer, a lower surface of at least a part of the lower wiring layer being covered by the lower insulating layer, a plurality of via plugs extending in a first direction on the lower wiring layer, the plurality of via plugs including a real via plug and a first dummy via plug connected to the part of the lower wiring layer covered by the lower insulating layer, and an upper wiring layer overlapping the lower wiring layer and extending in a second direction different from the first direction on the real via plug, the upper wiring layer not overlapping the dummy via plug.

Abstract: In a method of manufacturing an MRAM device, a lower electrode, a first pinning layer pattern, a tunnel barrier layer pattern and a free layer pattern sequentially stacked on a substrate may be formed. A first insulating interlayer may be formed on the substrate to cover the lower electrode, the first pinning layer pattern, the tunnel barrier layer pattern and the free layer pattern. The first insulating interlayer may be etched to form a recess exposing a top surface of the free layer pattern. A second pinning layer pattern may be formed to fill at least a portion of the recess. A wiring may be formed on the second pinning layer pattern.

Abstract: A nonvolatile memory device includes a bottom electrode on a semiconductor substrate, a data storage layer on the bottom electrode, the data storage layer including a transition metal oxide, and a switching layer provided on a top surface and/or a bottom surface of the data storage layer, wherein a bond energy of material included in the switching layer and oxygen is more than a bond energy of a transition metal in the transition metal oxide and oxygen.

Abstract: In a method of manufacturing an MRAM device, a lower electrode, a first pinning layer pattern, a tunnel barrier layer pattern and a free layer pattern sequentially stacked on a substrate may be formed. A first insulating interlayer may be formed on the substrate to cover the lower electrode, the first pinning layer pattern, the tunnel barrier layer pattern and the free layer pattern. The first insulating interlayer may be etched to form a recess exposing a top surface of the free layer pattern. A second pinning layer pattern may be formed to fill at least a portion of the recess. A wiring may be formed on the second pinning layer pattern.

Abstract: In a method of writing data in an MRAM device, a first operation unit is selected in a plurality of memory cells of the MRAM device. First to n-th switching pulses are sequentially applied to the first operation unit to write data in first to n-th groups of memory cells of the first operation unit, respectively. The n-th switching pulse may have a current level lower than that of an (n?1)th switching pulse, where n is an integer larger than at least 1. The n-th switching pulse may have a pulse width narrower than that of an (n?1)th switching pulse, where n is an integer larger than at least 1. The technique can be repeated for a second operation unit. A device and system are disclosed in which different current switching pulses are applied to multiple groups of memory cells within the first and/or second operation units.

Abstract: In a method of forming a magnetic pattern, a lower electrode layer is formed on a substrate. An insulating interlayer is formed on the lower electrode layer. The insulating interlayer is partially removed to form an opening. A first pinned layer pattern filling the opening is formed. A second pinned layer, a tunnel barrier layer, a free layer and an upper electrode layer are formed on the insulating interlayer and the first pinned layer pattern. The upper electrode layer, the free layer, the tunnel barrier layer and the second pinned layer are patterned to form a second pinned layer pattern, a tunnel barrier pattern, a free layer pattern and an upper electrode. The second pinned layer pattern covers an upper surface of the first pinned layer pattern.

Abstract: A swarm robot and a sweeping method using the swarm robot are provided. The swarm robot removes a plurality of objects in a given sweeping area, and at least two swarm robots collaborate to remove the individual object. The swarm robot searches the sweeping area, detects environment information of the sweeping area, locates the swarm robot in the sweeping area, generates a local map and an object map using the environment information and the acquired position, moves to the object according to the local map and the object map, and removes the object.

Abstract: An imaging apparatus includes: a rotator having a shape of a perforated circular plate and rotating around a rotating axis of a center of the perforated circular plate; and a supporter having a perforated circular plate and one side of which is connected to one side of the rotator such that the rotator is restricted only to rotation movement. The supporter includes a supporter opening/closing part a part of which is separated along the rotating axis and then rotates by a predetermined angle around the rotating axis, and the rotator includes a rotator opening/closing part a part of which integrally moves with the supporter opening/closing part.

Abstract: A nonvolatile memory device includes a bottom electrode on a semiconductor substrate, a data storage layer on the bottom electrode, the data storage layer including a transition metal oxide, and a switching layer provided on a top surface and/or a bottom surface of the data storage layer, wherein a bond energy of material included in the switching layer and oxygen is more than a bond energy of a transition metal in the transition metal oxide and oxygen.

Abstract: A nonvolatile memory device includes a bottom electrode on a semiconductor substrate, a data storage layer on the bottom electrode, the data storage layer including a transition metal oxide, and a switching layer provided on a top surface and/or a bottom surface of the data storage layer, wherein a bond energy of material included in the switching layer and oxygen is more than a bond energy of a transition metal in the transition metal oxide and oxygen.

Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate, the interlayer insulating layer comprising an opening exposing the substrate, a barrier layer pattern disposed within the opening, and a conductive pattern disposed on the barrier layer pattern, the conductive pattern having an oxidized portion extending out of the opening and a non-oxidized portion within the opening, wherein a width of the conductive pattern is determined by a thickness of the barrier layer pattern.

Abstract: The present invention relates to a stage, particularly to, a stage which is able to move minutely, having a rigidity-improved transfer part. A stage includes a work table on which a working object is placed, a motor configured to provide a rotational force, a shaft rotated by the motor to transfer the work table, a linear moving part configured to be expandable to linearly move the shaft in an axial direction, the linear moving part having a hollow to insert an end of the shaft therein, and an expanding part configured to be expandable as far as the shaft is moved by the linear moving part.

Abstract: A Resistance based Random Access Memory (ReRAM) can include a sense amplifier circuit that includes a first input coupled to a bit line of a reference cell in a first block of the ReRAM responsive to a read operation to a second block.

Abstract: In a method of writing data in an MRAM device, a first operation unit is selected in a plurality of memory cells of the MRAM device. First to n-th switching pulses are sequentially applied to the first operation unit to write data in first to n-th groups of memory cells of the first operation unit, respectively. The n-th switching pulse may have a current level lower than that of an (n?1)th switching pulse, where n is an integer larger than at least 1. The n-th switching pulse may have a pulse width narrower than that of an (n?1)th switching pulse, where n is an integer larger than at least 1. The technique can be repeated for a second operation unit. A device and system are disclosed in which different current switching pulses are applied to multiple groups of memory cells within the first and/or second operation units.

Abstract: In a method of forming a magnetic pattern, a lower electrode layer is formed on a substrate. An insulating interlayer is formed on the lower electrode layer. The insulating interlayer is partially removed to form an opening. A first pinned layer pattern filling the opening is formed. A second pinned layer, a tunnel barrier layer, a free layer and an upper electrode layer are formed on the insulating interlayer and the first pinned layer pattern. The upper electrode layer, the free layer, the tunnel barrier layer and the second pinned layer are patterned to form a second pinned layer pattern, a tunnel barrier pattern, a free layer pattern and an upper electrode. The second pinned layer pattern covers an upper surface of the first pinned layer pattern.