Abstract: A bitmap manager, a method of allocating a bitmap memory, a method of generating an acknowledgement between network entities, and a network entity implementing the same. The bitmap manager may include a bitmap memory for storing a block acknowledge of received frames based on a bitmap, a bitmap management information controller for receiving a bitmap entry number and storing bitmap management information associated with the physical address of the bitmap memory, and a bitmap manager finite state machine (BM FSM), receiving an update or an extract request for the received frames, managing the bitmap management information, and updating or extracting the bitmap memory.

Abstract: In a method and apparatus for data transmission suitable for a high-performance wireless LAN, the apparatus utilizes a serial communication interface device to perform data transmission between a master and a slave. The data transmission apparatus includes a data input unit for receiving at least one of transmission rate data and transmission length data to be transmitted from the master to the slave. A selection unit receives the at least one of the transmission rate data and the transmission length data from the data input unit, and receives at least one of a corresponding first event signal and a second event signal for selectively transmitting at least one of the transmission rate data and the transmission length data respectively to the slave.

Abstract: A security circuit using at least two finite state machine units for storing data to and reading data from a multiport memory in a pipelined manner and an intermediate memory, for facilitating transfer of data between the at least two finite state machines. The security circuit may be used to perform key setup and/or data ciphering faster. The security circuit may operate in any environment where the key is changed every frame, for example, a wireless LAN application and the security circuit may operate in conjunction with, or as part of, a MAC controller.

Abstract: A bitmap manager, a method of allocating a bitmap memory, a method of generating an acknowledgement between network entities, and a network entity implementing the same. The bitmap manager may include a bitmap memory for storing a block acknowledge of received frames based on a bitmap, a bitmap management information controller for receiving a bitmap entry number and storing bitmap management information associated with the physical address of the bitmap memory, and a bitmap manager finite state machine (BM FSM), receiving an update or an extract request for the received frames, managing the bitmap management information, and updating or extracting the bitmap memory.

Abstract: The present invention relates to a method for manufacturing a nano-structured metal oxide electrode, and in particular, to a method for manufacturing a metal oxide electrode having a few tens or hundreds of nanometers in diameter that is well adapted to an electrode of a supercapacitor using an alumina or polymer membrane having nano-sized pores as a template.

Abstract: An apparatus and method are provided for manufacturing an electrode of hydrous ruthenium oxide thin film, consisting of an injector for spraying a precursor solution, a substrate for depositing the precursor solution, a base for supporting the substrate and a halogen lamp for heating the substrate, a DC power supply connected to the injector and base, a space adjuster for adjusting the spraying space between the injector and the base, and temperature controller for controlling the temperature of the base. Because of the strong electric field, the sprayed ruthenium precursor solution atomizes the nano-sized very fine particles. Therefore, the atomized particles are deposited on the substrate to form a very fine porous thin film under the influence of electrically charged molecular actions without the influence of gravitation force. The ruthenium oxide electrode formed the fine porous thin film has excellent property of super capacitor, composite electrode of ruthenium oxide and activated carbon.

Abstract: In a method and apparatus for data transmission suitable for a high-performance wireless LAN, the apparatus utilizes a serial communication interface device to perform data transmission between a master and a slave. The data transmission apparatus includes a data input unit for receiving at least one of transmission rate data and transmission length data to be transmitted from the master to the slave. A selection unit receives the at least one of the transmission rate data and the transmission length data from the data input unit, and receives at least one of a corresponding first event signal and a second event signal for selectively transmitting at least one of the transmission rate data and the transmission length data respectively to the slave.

Abstract: A method of block-level encryption/decryption for an offset codebook mode of operation during transmission/reception can include: receiving a frame of data to encrypted/decrypted; beginning to divide the frame into at least two packets before receipt of the frame is completed; beginning to divide at least one of the packets into two or more blocks before receipt of the frame is completed; releasing the blocks of the at least one packet for encryption/decryption before receipt of the frame is completed; and enciphering/deciphering the blocks of the at least one packet before receipt of the frame is completed.

Abstract: The present invention relates to a cryptographic apparatus for encrypting data stored in a memory. The cryptographic apparatus of the present invention operates in the ECB, CBC, BCB-MAC, counter and OCB modes using small and simple elements. The cryptographic apparatus minimizes data communication between CPU and the cryptographic apparatus to improve the performance of the communication system. On the other hand, the input buffer and output buffer of the cryptographic apparatus are configured to store at least two blocks respectively, so that the performance of the cryptographic apparatus is maximized. Furthermore, the cryptographic apparatus supports zero-padding, so that the process of the CPU is minimized.