Patents by Inventor Kyung-yub Jeon
Kyung-yub Jeon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11443988Abstract: A method for manufacturing a semiconductor is provided. A first oxide layer is formed on a substrate. A first nitride layer is formed on the first oxide layer. A second oxide layer, a second nitride layer are formed on the first nitride layer. A polysilicon layer is formed on the second nitride layer. A third nitride layer is formed on the polysilicon layer. One or more first patterns are formed on the third nitride layer. The one or more first patterns are transferred to the polysilicon layer to form one or more patterned polysilicon layer. A portion of the first oxide layer, first nitride layer, second oxide layer, and second nitride layer are removed using the one or more patterned polysilicon layer as a first mask.Type: GrantFiled: September 30, 2020Date of Patent: September 13, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Kyung Yub Jeon
-
Publication number: 20210020523Abstract: A method for manufacturing a semiconductor is provided. A first oxide layer is formed on a substrate. A first nitride layer is formed on the first oxide layer. A second oxide layer, a second nitride layer are formed on the first nitride layer. A polysilicon layer is formed on the second nitride layer. A third nitride layer is formed on the polysilicon layer. One or more first patterns are formed on the third nitride layer. The one or more first patterns are transferred to the polysilicon layer to form one or more patterned polysilicon layer. A portion of the first oxide layer, first nitride layer, second oxide layer, and second nitride layer are removed using the one or more patterned polysilicon layer as a first mask.Type: ApplicationFiled: September 30, 2020Publication date: January 21, 2021Inventor: KYUNG YUB JEON
-
Patent number: 10892347Abstract: A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.Type: GrantFiled: November 21, 2018Date of Patent: January 12, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Kyung Yub Jeon, Tae Yong Kwon, Oh Seong Kwon, Soo Yeon Jeong, Yong Hee Park, Jong Ryeol Yoo
-
Patent number: 10840150Abstract: A method for manufacturing a semiconductor is provided. A first oxide layer is formed on a substrate. A first nitride layer is formed on the first oxide layer. A second oxide layer, a second nitride layer are formed on the first nitride layer. A polysilicon layer is formed on the second nitride layer. A third nitride layer is formed on the polysilicon layer. One or more first patterns are formed on the third nitride layer. The one or more first patterns are transferred to the polysilicon layer to form one or more patterned polysilicon layer. A portion of the first oxide layer, first nitride layer, second oxide layer, and second nitride layer are removed using the one or more patterned polysilicon layer as a first mask.Type: GrantFiled: December 15, 2017Date of Patent: November 17, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Kyung Yub Jeon
-
Patent number: 10804160Abstract: A method for manufacturing a semiconductor device is provided. A first vertical structure and a second vertical structure are formed on a substrate. The second vertical structure is positioned right next to the first vertical structure. The second vertical structure is positioned right next to the first vertical structure. An insulating layer is formed on the substrate between the first and second vertical structures. A gate metal and a gate dielectric layer, are formed on the first and second vertical structures. A portion of the gate metal, gate dielectric layer, and insulating layer is removed. A portion of the substrate is removed. The portion of the substrate is removed after the gate metal is formed on the first and second vertical structure.Type: GrantFiled: July 10, 2019Date of Patent: October 13, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyung Yub Jeon, Soo Yeon Jeong, Jae Kwang Choi
-
Patent number: 10566326Abstract: Semiconductor devices are provided. A semiconductor device includes a semiconductor substrate. The semiconductor device includes first and second source/drain regions in the semiconductor substrate. Moreover, the semiconductor device includes a multi-layer device isolation region in the semiconductor substrate between the first and second source/drain regions. The multi-layer device isolation region includes a protruding portion that protrudes away from the semiconductor substrate beyond respective uppermost surfaces of the first and second source/drain regions.Type: GrantFiled: July 6, 2017Date of Patent: February 18, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Dae Young Kwak, Ki Byung Park, Kyoung Hwan Yeo, Seung Jae Lee, Kyung Yub Jeon, Seung Seok Ha, Sang Jin Hyun
-
Patent number: 10566207Abstract: A method for defining a length of a fin including forming a plurality of first slice walls on a mask material layer, which is provided over the fin, using a plurality of hard mask patterns, providing a plurality of fill mask patterns self-aligned with respect to the plurality of first slice walls to expose one or more select areas between one or more pairs of adjacent ones of the plurality of first slice walls, and providing a trim mask pattern including one or more openings and self-aligned with respect to the plurality of second slice walls to expose one or more of the plurality of first slice walls may be provided.Type: GrantFiled: September 19, 2018Date of Patent: February 18, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Gyeongseop Kim, Kyung Yub Jeon, Seul Gi Han
-
Publication number: 20190333825Abstract: A method for manufacturing a semiconductor device is provided. A first vertical structure and a second vertical structure are formed on a substrate. The second vertical structure is positioned right next to the first vertical structure. The second vertical structure is positioned right next to the first vertical structure. An insulating layer is formed on the substrate between the first and second vertical structures. A gate metal and a gate dielectric layer, are formed on the first and second vertical structures. A portion of the gate metal, gate dielectric layer, and insulating layer is removed. A portion of the substrate is removed. The portion of the substrate is removed after the gate metal is formed on the first and second vertical structure.Type: ApplicationFiled: July 10, 2019Publication date: October 31, 2019Inventors: Kyung Yub Jeon, Soo Yeon Jeong, Jae Kwang Choi
-
Patent number: 10373878Abstract: A method for manufacturing a semiconductor device is provided. A first vertical structure and a second vertical structure are formed on a substrate. The second vertical structure is positioned right next to the first vertical structure. The second vertical structure is positioned right next to the first vertical structure. An insulating layer is formed on the substrate between the first and second vertical structures. A gate metal and a gate dielectric layer are formed on the first and second vertical structures. A portion of the gate metal, gate dielectric layer, and insulating layer is removed. A portion of the substrate is removed. The portion of the substrate is removed after the gate metal is formed on the first and second vertical structure.Type: GrantFiled: December 26, 2017Date of Patent: August 6, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyung Yub Jeon, Soo Yeon Jeong, Jae Kwang Choi
-
Publication number: 20190198340Abstract: A method for defining a length of a fin including forming a plurality of first slice walls on a mask material layer, which is provided over the fin, using a plurality of hard mask patterns, providing a plurality of fill mask patterns self-aligned with respect to the plurality of first slice walls to expose one or more select areas between one or more pairs of adjacent ones of the plurality of first slice walls, and providing a trim mask pattern including one or more openings and self-aligned with respect to the plurality of second slice walls to expose one or more of the plurality of first slice walls may be provided.Type: ApplicationFiled: September 19, 2018Publication date: June 27, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Gyeongseop KIM, Kyung Yub JEON, Seul Gi HAN
-
Publication number: 20190109214Abstract: A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.Type: ApplicationFiled: November 21, 2018Publication date: April 11, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Kyung Yub JEON, Tae Yong KWON, Oh Seong KWON, Soo Yeon JEONG, Yong Hee PARK, Jong Ryeol YOO
-
Patent number: 10164057Abstract: A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.Type: GrantFiled: January 24, 2018Date of Patent: December 25, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Kyung Yub Jeon, Tae Yong Kwon, Oh Seong Kwon, Soo Yeon Jeong, Yong Hee Park, Jong Ryeol Yoo
-
Publication number: 20180350952Abstract: A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.Type: ApplicationFiled: January 24, 2018Publication date: December 6, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Kyung Yub JEON, Tae Yong KWON, Oh Seong KWON, Soo Yeon JEONG, Yong Hee PARK, Jong Ryeol YOO
-
Publication number: 20180315662Abstract: A method for manufacturing a semiconductor device is provided. A first vertical structure and a second vertical structure are formed on a substrate. The second vertical structure is positioned right next to the first vertical structure. The second vertical structure is positioned right next to the first vertical structure. An insulating layer is formed on the substrate between the first and second vertical structures. A gate metal and a gate dielectric layer are formed on the first and second vertical structures. A portion of the gate metal, gate dielectric layer, and insulating layer is removed. A portion of the substrate is removed. The portion of the substrate is removed after the gate metal is formed on the first and second vertical structure.Type: ApplicationFiled: December 26, 2017Publication date: November 1, 2018Inventors: KYUNG YUB JEON, Soo Yeon Jeong, Jae Kwang Choi
-
Publication number: 20180197790Abstract: A method for manufacturing a semiconductor is provided. A first oxide layer is formed on a substrate. A first nitride layer is formed on the first oxide layer. A second oxide layer, a second nitride layer are formed on the first nitride layer. A polysilicon layer is formed on the second nitride layer. A third nitride layer is formed on the polysilicon layer. One or more first patterns are formed on the third nitride layer. The one or more first patterns are transferred to the polysilicon layer to form one or more patterned polysilicon layer. A portion of the first oxide layer, first nitride layer, second oxide layer, and second nitride layer are removed using the one or more patterned polysilicon layer as a first mask.Type: ApplicationFiled: December 15, 2017Publication date: July 12, 2018Inventor: KYUNG YUB JEON
-
Publication number: 20180090493Abstract: Semiconductor devices are provided. A semiconductor device includes a semiconductor substrate. The semiconductor device includes first and second source/drain regions in the semiconductor substrate. Moreover, the semiconductor device includes a multi-layer device isolation region in the semiconductor substrate between the first and second source/drain regions. The multi-layer device isolation region includes a protruding portion that protrudes away from the semiconductor substrate beyond respective uppermost surfaces of the first and second source/drain regions.Type: ApplicationFiled: July 6, 2017Publication date: March 29, 2018Inventors: Dae Young Kwak, Ki Byung Park, Kyoung Hwan Yeo, Seung Jae Lee, Kyung Yub Jeon, Seung Seok Ha, Sang Jin Hyun
-
Patent number: 9899497Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming an active pattern protruding orthogonally from a substrate; forming a preliminary gate structure on the active pattern to cross the active pattern; etching the active pattern to form preliminary recess regions at both sides of the preliminary gate structure, wherein each of the preliminary recess regions is formed to define a delta region in an upper portion of the active pattern; forming a sacrificial layer on inner side surfaces and a bottom surface of the active pattern exposed by each of the preliminary recess regions; etching the delta regions and the sacrificial layer to form recess regions having a āUā-shaped section; and forming source/drain regions in the recess regions.Type: GrantFiled: November 18, 2016Date of Patent: February 20, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jin Bum Kim, Kang Hun Moon, Choeun Lee, Kyung Yub Jeon, Sujin Jung, Haegeon Jung, Yang Xu
-
Patent number: 9754770Abstract: To diagnose plasma in a plasma space, a plurality of floating probes are installed at a plurality of points, respectively, in a plasma space. An electron density ratio at each of the points is calculated by measuring a first probe current of each of the floating probes, the probe current including a DC component. A point ion density and a point electron temperature at each of the points are calculated by measuring a second probe current of each of the floating probes before the electron density ratio is calculated, the second probe current excluding the DC component.Type: GrantFiled: March 7, 2014Date of Patent: September 5, 2017Assignees: Samsung Electronics Co., Ltd., Industry-University Cooperation Foundation Hanyang UniversityInventors: Kyung-Yub Jeon, Jeong-Yun Lee, Chin-Wook Chung
-
Publication number: 20170162674Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming an active pattern protruding orthogonally from a substrate; forming a preliminary gate structure on the active pattern to cross the active pattern; etching the active pattern to form preliminary recess regions at both sides of the preliminary gate structure, wherein each of the preliminary recess regions is formed to define a delta region in an upper portion of the active pattern; forming a sacrificial layer on inner side surfaces and a bottom surface of the active pattern exposed by each of the preliminary recess regions; etching the delta regions and the sacrificial layer to form recess regions having a āUā-shaped section; and forming source/drain regions in the recess regions.Type: ApplicationFiled: November 18, 2016Publication date: June 8, 2017Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jin Bum KIM, Kang Hun MOON, Choeun LEE, Kyung Yub JEON, Sujin JUNG, Haegeon JUNG, Yang XU
-
Patent number: 9607853Abstract: A patterning method using a metal mask includes sequentially forming a lower metal layer and an upper metal layer on an etching object layer, forming an upper metal mask, forming the upper metal mask including patterning the upper metal layer, forming a lower metal mask, forming the lower metal mask including patterning the lower metal layer using the upper metal mask, and patterning the etching object layer using the upper metal mask.Type: GrantFiled: March 12, 2015Date of Patent: March 28, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Kyung-yub Jeon, Dong-chan Kim, Gyung-jin Min, Jae-hong Park, Je-woo Han