Abstract: The present invention provides methods for treating or ameliorating metabolic diseases, cholestatic liver diseases, or organ fibrosis, which comprises administering to a subject a therapeutically effective amount of a pharmaceutical composition comprising an isoxazole derivative, a racemate, an enantiomer, or a diastereoisomer thereof, or a pharmaceutically acceptable salt of the derivative, the racemate, the enantiomer, or the diastereoisomer.

Abstract: Image processor circuitry includes a memory storing a program of instructions, and processing circuitry configured to execute the program of instructions to receive input data from an image sensor and detect an operation mode of the image sensor based on the input data, provide configuration data determined in association with the operation mode of the image sensor, and process image data in the input data in accordance with the operation mode and the configuration data.

Abstract: Image processor circuitry includes a memory storing a program of instructions, and processing circuitry configured to execute the program of instructions to receive input data from an image sensor and detect an operation mode of the image sensor based on the input data, provide configuration data determined in association with the operation mode of the image sensor, and process image data in the input data in accordance with the operation mode and the configuration data.

Abstract: An image processor is provided. In some examples, the image processor is in a system on chip or part of a larger image processing system. The image processor may include an application processor, a codec module, and a memory controller, and in some examples may also function with a dithering unit, a display controller, a display, and/or a CMOS image sensor. The image processor processes, stores, and reads image data using an embedded memory and/or an external memory. The image data is comprised of a plurality of pixels, each of which may include a first and second set of bits that can be separately or simultaneously accessed at the memory in a first and second region of the memory using one or more addresses. The first set of bits may correspond to the more significant bits of each pixel and the second set of bits may correspond to the less significant bits.

Abstract: An image processing system comprises a first image processing device configured to process a frame of image data comprising a plurality of pixels, each having corresponding pixel values. Each of the pixel values include a first and second set of bits that may be separately or simultaneously accessed and/or processed. The first set of bits may correspond to the more significant bits of each pixel and the second set of bits may correspond to the less significant bits. In some examples the number of bits in each of the first and second set of bits may correspond to the width of a used data bus and/or features of a peripheral device connected to the image processor, such as a display.

Abstract: Provided is an image processing device configured to compress first image data. The image processing device includes an encoding circuit configured to compress the first image data into second image data including prediction data and residual data, compress the second image data into third image data by performing entropy encoding on the second image data, generate a header representing a compression ratio of the third image data, and store the third image data along with the header in a memory device as compressed first image data.

Abstract: Image processor circuitry includes a memory storing a program of instructions, and processing circuitry configured to execute the program of instructions to receive input data from an image sensor and detect an operation mode of the image sensor based on the input data, provide configuration data determined in association with the operation mode of the image sensor, and process image data in the input data in accordance with the operation mode and the configuration data.

Abstract: Provided is an image processing device configured to compress first image data. The image processing device includes an encoding circuit configured to compress the first image data into second image data including prediction data and residual data, compress the second image data into third image data by performing entropy encoding on the second image data, generate a header representing a compression ratio of the third image data, and store the third image data along with the header in a memory device as compressed first image data.

Abstract: Image processor circuitry includes a memory storing a program of instructions, and processing circuitry configured to execute the program of instructions to receive input data from an image sensor and detect an operation mode of the image sensor based on the input data, provide configuration data determined in association with the operation mode of the image sensor, and process image data in the input data in accordance with the operation mode and the configuration data.

Abstract: An image processor is provided. In some examples, the image processor is in a system on chip or part of a larger image processing system. The image processor may include an application processor, a codec module, and a memory controller, and in some examples may also function with a dithering unit, a display controller, a display, and/or a CMOS image sensor. The image processor processes, stores, and reads image data using an embedded memory and/or an external memory. The image data is comprised of a plurality of pixels, each of which may include a first and second set of bits that can be separately or simultaneously accessed at the memory in a first and second region of the memory using one or more addresses. The first set of bits may correspond to the more significant bits of each pixel and the second set of bits may correspond to the less significant bits.

Abstract: Image processor circuitry includes a memory storing a program of instructions, and processing circuitry configured to execute the program of instructions to receive input data from an image sensor and detect an operation mode of the image sensor based on the input data, provide configuration data determined in association with the operation mode of the image sensor, and process image data in the input data in accordance with the operation mode and the configuration data.

Abstract: A method of processing image data comprises processing a frame of image data comprising a plurality of pixels, each having corresponding pixel values. Each of the pixel values include a first and second set of bits that may be separately or simultaneously accessed and/or processed. The first set of bits may correspond to the more significant bits of each pixel and the second set of bits may correspond to the less significant bits. In some examples the number of bits in each of the first and second set of bits may correspond to the width of a used data bus and/or features of a peripheral device connected to the image processor, such as a display.

Abstract: A wireless display subsystem includes a hardware composition generator, a hardware video encoder, and a wireless hardware transport stream multiplexer. The hardware composition generator reads video data from a memory device and generates video frame data by synthesizing the video data. The hardware video encoder receives the video frame data in an on-the-fly (OTF) manner from the hardware composition generator and generates a video stream by encoding the video frame data. The wireless hardware transport stream multiplexer receives the video stream in the OTF manner from the hardware video encoder, reads an audio stream from the memory device, multiplexes the video stream and the audio stream, and generates a wireless display packet by packetizing the multiplexed video and audio streams.

Abstract: Provided is an image processing device configured to compress first image data. The image processing device includes an encoding circuit configured to compress the first image data into second image data including prediction data and residual data, compress the second image data into third image data by performing entropy encoding on the second image data, generate a header representing a compression ratio of the third image data, and store the third image data along with the header in a memory device as compressed first image data.

Abstract: An image processor is provided. In some examples, the image processor is in a system on chip or part of a larger image processing system. The image processor may include an application processor, a codec module, and a memory controller, and in some examples may also function with a dithering unit, a display controller, a display, and/or a CMOS image sensor. The image processor processes, stores, and reads image data using an embedded memory and/or an external memory. The image data is comprised of a plurality of pixels, each of which may include a first and second set of bits that can be separately or simultaneously accessed at the memory in a first and second region of the memory using one or more addresses. The first set of bits may correspond to the more significant bits of each pixel and the second set of bits may correspond to the less significant bits.

Abstract: A wireless display subsystem includes a hardware composition generator, a hardware video encoder, and a wireless hardware transport stream multiplexer. The hardware composition generator reads video data from a memory device and generates video frame data by synthesizing the video data. The hardware video encoder receives the video frame data in an on-the-fly (OTF) manner from the hardware composition generator and generates a video stream by encoding the video frame data. The wireless hardware transport stream multiplexer receives the video stream in the OTF manner from the hardware video encoder, reads an audio stream from the memory device, multiplexes the video stream and the audio stream, and generates a wireless display packet by packetizing the multiplexed video and audio streams.

Abstract: An image processor processes a plurality of pixels. Each of the pixels include a first and second set of bits that can be separately or simultaneously in first and second regions of a memory using one or more addresses. The first set of bits may correspond to the more significant bits of each pixel and the second set of bits may correspond to the less significant bits. In some examples the number of bits in each of the first and second set of bits may be selected according to the width of a used data bus and/or features of a peripheral device connected to the image processor such as a display.

Abstract: An image processor is provided. In some examples, the image processor is in a system on chip or part of a larger image processing system. The image processor may include an application processor, a codec module, and a memory controller, and in some examples may also function with a dithering unit, a display controller, a display, and/or a CMOS image sensor. The image processor processes, stores, and reads image data using an embedded memory and/or an external memory. The image data is comprised of a plurality of pixels, each of which may include a first and second set of bits that can be separately or simultaneously accessed at the memory in a first and second region of the memory using one or more addresses. The first set of bits may correspond to the more significant bits of each pixel and the second set of bits may correspond to the less significant bits.

Abstract: A method of manufacturing a semiconductor device in which a source contact plug and a drain contact plug are formed. The method includes the steps of etching part of the semiconductor substrate to form a step, thus forming an overlay vernier, and forming a hard mask on the step so that the step is maintained.

Abstract: The data interface device accesses a memory operating in synchronization with a clock. A board clock and selective data capturing improve the operating rate of a memory interface and time-synchronize data flow from memory to memory controller with a internal clock produced by the memory controller; or time-synchronize data flow from the memory controller with the board clock. The internal clock is passed through a sequential path of an output pad of the memory controller, the memory, and an input pad of the memory controller and then re-inputted into the memory controller thereby the feedback clock is generated. The selective data capturing uses a register part for storing data inputted into the memory controller. The register part for storing the data is configured by double registers that are operated in an alternative manner according to a correlation between the inputted data and the feedback clock.