Patents by Inventor KYUNGHWA YUN
KYUNGHWA YUN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11875855Abstract: A memory device including: a memory cell array disposed in a first semiconductor layer, the memory cell array including a plurality of wordlines extended in a first direction and stacked in a second direction substantially perpendicular to the first direction; and a plurality of pass transistors disposed in the first semiconductor layer, wherein a first pass transistor of the plurality of pass transistors is disposed between a first signal line of a plurality of signal lines and a first wordline of the plurality of wordlines, and wherein the plurality of signal lines are arranged at the same level as a common source line.Type: GrantFiled: May 17, 2022Date of Patent: January 16, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyunghwa Yun, Chanho Kim, Pansuk Kwak
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Patent number: 11723208Abstract: A memory device comprises a peripheral circuit region including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder, and a memory cell region including a cell array region and a cell contact region, wherein the cell array region includes wordlines, stacked on a second substrate on the peripheral circuit region, and channel structures extending in a direction perpendicular to an upper surface of the second substrate and penetrating the wordlines, wherein the cell contact region includes cell contacts connected to the wordlines and on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths to each other in the first direction, wherein each of the first and second cell contact regions includes first pads having different lengths than each other inType: GrantFiled: March 15, 2022Date of Patent: August 8, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyunghwa Yun, Pansuk Kwak, Chanho Kim, Dongku Kang
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Publication number: 20220352204Abstract: A nonvolatile memory device includes a peripheral circuit including a first active region and a memory block including a second active region on the peripheral circuit. The memory block includes a vertical structure including pairs of a first insulating layer and a first conductive layer, a second insulating layer on the vertical structure, a second conductive layer and a third conductive layer spaced apart from each other on the second insulating layer, first vertical channels and second vertical channels. The second conductive layer and the third conductive layer are connected with a first through via penetrating the vertical structure, the second active region, and a region of the second insulating layer that is exposed between the second conductive layer and the third conductive layer.Type: ApplicationFiled: July 8, 2022Publication date: November 3, 2022Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyunghwa YUN, Chanho Kim, Dongku Kang
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Publication number: 20220277792Abstract: A memory device including: a memory cell array disposed in a first semiconductor layer, the memory cell array including a plurality of wordlines extended in a first direction and stacked in a second direction substantially perpendicular to the first direction; and a plurality of pass transistors disposed in the first semiconductor layer, wherein a first pass transistor of the plurality of pass transistors is disposed between a first signal line of a plurality of signal lines and a first wordline of the plurality of wordlines, and wherein the plurality of signal lines are arranged at the same level as a common source line.Type: ApplicationFiled: May 17, 2022Publication date: September 1, 2022Inventors: Kyunghwa Yun, Chanho Kim, Pansuk Kwak
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Patent number: 11430806Abstract: A nonvolatile memory device includes a peripheral circuit including a first active region and a memory block including a second active region on the peripheral circuit. The memory block includes a vertical structure including pairs of a first insulating layer and a first conductive layer, a second insulating layer on the vertical structure, a second conductive layer and a third conductive layer spaced apart from each other on the second insulating layer, first vertical channels and second vertical channels. The second conductive layer and the third conductive layer are connected with a first through via penetrating the vertical structure, the second active region, and a region of the second insulating layer that is exposed between the second conductive layer and the third conductive layer.Type: GrantFiled: May 20, 2020Date of Patent: August 30, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyunghwa Yun, Chanho Kim, Dongku Kang
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Patent number: 11430804Abstract: A vertical memory device is provided. The vertical memory device includes gate electrodes formed on a substrate and spaced apart from each other in a first direction substantially perpendicular to an upper surface of the substrate, the gate electrodes including a first gate electrode and a second gate electrode that is interposed between the first gate electrode and the substrate; a channel extending through the gate electrodes in the first direction; an insulating isolation pattern extending through the first gate electrode in the first direction, and spaced apart from the first gate electrode in a second direction substantially parallel to the upper surface of the substrate; and a blocking pattern disposed on an upper surface, a lower surface and a sidewall of each of the gate electrodes, the sidewall of the gate electrodes facing the channel. The insulating isolation pattern directly contacts the first gate electrode.Type: GrantFiled: March 4, 2020Date of Patent: August 30, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyunghwa Yun, Chanho Kim, Dongku Kang
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Publication number: 20220208784Abstract: A memory device comprises a peripheral circuit region including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder, and a memory cell region including a cell array region and a cell contact region, wherein the cell array region includes wordlines, stacked on a second substrate on the peripheral circuit region, and channel structures extending in a direction perpendicular to an upper surface of the second substrate and penetrating the wordlines, wherein the cell contact region includes cell contacts connected to the wordlines and on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths to each other in the first direction, wherein each of the first and second cell contact regions includes first pads having different lengths than each other inType: ApplicationFiled: March 15, 2022Publication date: June 30, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Kyunghwa YUN, Pansuk KWAK, Chanho KIM, Dongku KANG
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Patent number: 11355194Abstract: A memory device including: a memory cell array disposed in a first semiconductor layer, the memory cell array including a plurality of wordlines extended in a first direction and stacked in a second direction substantially perpendicular to the first direction; and a plurality of pass transistors disposed in the first semiconductor layer, wherein a first pass transistor of the plurality of pass transistors is disposed between a first signal line of a plurality of signal lines and a first wordline of the plurality of wordlines, and wherein the plurality of signal lines are arranged at the same level as a common source line.Type: GrantFiled: July 29, 2020Date of Patent: June 7, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyunghwa Yun, Chanho Kim, Pansuk Kwak
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Patent number: 11348910Abstract: A non-volatile memory device includes a first semiconductor layer having a stair area and a cell area having a memory cell array formed therein, and a second semiconductor layer including a page buffer connected to the memory cell array. The first semiconductor layer includes a plurality of word lines, a ground selection line in a layer on the word lines, a common source line in a layer on the ground selection line, a plurality of vertical pass transistors in the stair area, and a plurality of driving signal lines in the same layer as the common source line. The word lines form a stair shape in the stair area, and each of the vertical pass transistors is connected between a corresponding one of the word lines and a corresponding one of the driving signal lines.Type: GrantFiled: April 30, 2020Date of Patent: May 31, 2022Inventors: Chanho Kim, Kyunghwa Yun, Daeseok Byeon
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Patent number: 11302396Abstract: A memory device includes a memory cell array, a row decoder connected to the memory cell array by a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines, and a common source line driver connected to the memory cell array by a common source line. The memory cell array is located in an upper chip, at least a portion of the row decoder is located in a lower chip, at least a portion of the common source line driver is located in the upper chip, and a plurality of upper bonding pads of the upper chip are connected to a plurality of lower bonding pads of the lower chip to connect the upper chip to the lower chip.Type: GrantFiled: April 29, 2020Date of Patent: April 12, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Taehong Kwon, Youngsun Min, Daeseok Byeon, Kyunghwa Yun
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Patent number: 11289500Abstract: A memory device comprises a peripheral circuit region including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder, and a memory cell region including a cell array region and a cell contact region, wherein the cell array region includes wordlines, stacked on a second substrate on the peripheral circuit region, and channel structures extending in a direction perpendicular to an upper surface of the second substrate and penetrating the wordlines, wherein the cell contact region includes cell contacts connected to the wordlines and on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths to each other in the first direction, wherein each of the first and second cell contact regions includes first pads having different lengths than each other inType: GrantFiled: August 24, 2020Date of Patent: March 29, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyunghwa Yun, Pansuk Kwak, Chanho Kim, Dongku Kang
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Patent number: 11289467Abstract: A memory device includes a memory cell array, a row decoder connected to the memory cell array by a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines, and a common source line driver connected to the memory cell array by a common source line. The memory cell array is located in an upper chip, at least a portion of the row decoder is located in a lower chip, at least a portion of the common source line driver is located in the upper chip, and a plurality of upper bonding pads of the upper chip are connected to a plurality of lower bonding pads of the lower chip to connect the upper chip to the lower chip.Type: GrantFiled: July 31, 2020Date of Patent: March 29, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Taehong Kwon, Youngsun Min, Daeseok Byeon, Kyunghwa Yun
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Publication number: 20220093629Abstract: A semiconductor device and an electronic system, the semiconductor device including a semiconductor substrate; a peripheral circuit structure including peripheral circuits integrated on the semiconductor substrate, and a landing pad connected to the peripheral circuits; a semiconductor layer on the peripheral circuit structure; a metal structure in contact with a portion of the semiconductor layer, the metal structure including first portions extending in a first direction, second portions connected to the first portions and extending in a second direction crossing the first direction, and a via portion vertically extending from at least one of the first and second portions and being connected to the landing pad; and a stack including insulating layers and electrodes vertically and alternately stacked on the metal structure.Type: ApplicationFiled: April 28, 2021Publication date: March 24, 2022Inventors: Junhyoung KIM, Chanho KIM, Kyunghwa YUN, Dongseong KIM
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Patent number: 11282827Abstract: A nonvolatile memory device includes a memory cell region including first metal pads, and a peripheral circuit region including second metal pads. The memory cell region includes a vertical structure including pairs of a first insulating layer and a first conductive layer, a second insulating layer on the vertical structure, a second conductive layer and a third conductive layer spaced apart from each other on the second insulating layer, first vertical channels and second vertical channels. The second conductive layer and the third conductive layer are connected with a first through via penetrating the vertical structure and a region of the second insulating layer that is exposed between the second conductive layer and the third conductive layer. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.Type: GrantFiled: July 27, 2020Date of Patent: March 22, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyunghwa Yun, Chanho Kim, Dongku Kang
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Patent number: 11211391Abstract: A memory device includes a peripheral circuit region including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder; a cell array region including wordlines, stacked on a second substrate on the peripheral circuit region, and channel structures extending in a direction perpendicular to an upper surface of the second substrate and penetrating through the wordlines; and a cell contact region including cell contacts connected to the wordlines and on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths to each other in the first direction.Type: GrantFiled: March 10, 2020Date of Patent: December 28, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyunghwa Yun, Pansuk Kwak, Chanho Kim, Dongku Kang
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Patent number: 11189634Abstract: A memory device including: a memory cell array disposed in a first semiconductor layer, the memory cell array including a plurality of wordlines extended in a first direction and stacked in a second direction substantially perpendicular to the first direction; and a plurality of pass transistors disposed in the first semiconductor layer, wherein a first pass transistor of the plurality of pass transistors is disposed between a first signal line of a plurality of signal lines and a first wordline of the plurality of wordlines, and wherein the plurality of signal lines are arranged at the same level as a common source line.Type: GrantFiled: December 6, 2019Date of Patent: November 30, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyunghwa Yun, Chanho Kim, Pansuk Kwak
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Patent number: 11087844Abstract: A non-volatile memory device includes a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a second metal pad and vertically connected to the memory cell region. The memory cell region includes a plurality of word lines, a ground selection line in a layer on the word lines, a common source line in a layer on the ground selection line, a plurality of vertical pass transistors in the stair area, and a plurality of driving signal lines in the same layer as the common source line. The word lines form a stair shape in the stair area, and each of the vertical pass transistors is connected between a corresponding one of the word lines and a corresponding one of the driving signal lines.Type: GrantFiled: July 31, 2020Date of Patent: August 10, 2021Inventors: Chanho Kim, Kyunghwa Yun, Daeseok Byeon
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Publication number: 20210118861Abstract: A nonvolatile memory device includes a memory cell region including first metal pads, and a peripheral circuit region including second metal pads. The memory cell region includes a vertical structure including pairs of a first insulating layer and a first conductive layer, a second insulating layer on the vertical structure, a second conductive layer and a third conductive layer spaced apart from each other on the second insulating layer, first vertical channels and second vertical channels. The second conductive layer and the third conductive layer are connected with a first through via penetrating the vertical structure and a region of the second insulating layer that is exposed between the second conductive layer and the third conductive layer. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.Type: ApplicationFiled: July 27, 2020Publication date: April 22, 2021Applicant: SAMSUNG ELECTRONICS CO, LTD.Inventors: Kyunghwa YUN, Chanho KIM, Dongku KANG
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Publication number: 20210118903Abstract: A nonvolatile memory device includes a peripheral circuit including a first active region and a memory block including a second active region on the peripheral circuit. The memory block includes a vertical structure including pairs of a first insulating layer and a first conductive layer, a second insulating layer on the vertical structure, a second conductive layer and a third conductive layer spaced apart from each other on the second insulating layer, first vertical channels and second vertical channels. The second conductive layer and the third conductive layer are connected with a first through via penetrating the vertical structure, the second active region, and a region of the second insulating layer that is exposed between the second conductive layer and the third conductive layer.Type: ApplicationFiled: May 20, 2020Publication date: April 22, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyunghwa Yun, Chanho Kim, Dongku Kang
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Publication number: 20210066281Abstract: A memory device includes a memory cell array, a row decoder connected to the memory cell array by a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines, and a common source line driver connected to the memory cell array by a common source line. The memory cell array is located in an upper chip, at least a portion of the row decoder is located in a lower chip, at least a portion of the common source line driver is located in the upper chip, and a plurality of upper bonding pads of the upper chip are connected to a plurality of lower bonding pads of the lower chip to connect the upper chip to the lower chip.Type: ApplicationFiled: July 31, 2020Publication date: March 4, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Taehong KWON, Youngsun MIN, Daeseok BYEON, Kyunghwa YUN