Patents by Inventor Kyung-Moon Kim
Kyung-Moon Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11970493Abstract: The present disclosure provides autotaxin (ATX) inhibitor compounds and compositions including said compounds. The present disclosure also provides methods of using said compounds and compositions for inhibiting ATX. Also provided are methods of preparing said compounds and compositions, and synthetic precursors of said compounds.Type: GrantFiled: October 4, 2021Date of Patent: April 30, 2024Assignee: ILDONG PHARMACEUTICAL CO., LTD.Inventors: Sung-Ku Choi, Yoon-Suk Lee, Sung-Wook Kwon, Kyung-Sun Kim, Jeong-Geun Kim, Jeong-Ah Kim, An-Na Moon, Sun-Young Park, Jun-Su Ban, Dong-Keun Song, Kyu-Sic Jang, Ju-Young Jung, Soo-Jin Lee
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Patent number: 11966544Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The display may include transistors with gate conductors, a first planarization layer formed over the gate conductors, one or more contacts formed in a first source-drain layer within the first planarization layer, a second planarization layer formed on the first planarization layer, one or more data lines formed in a second source-drain layer within the second planarization layer, a third planarization layer formed on the second planarization layer, and a data line shielding structure formed at least partly in a third source-drain layer within the third planarization layer. The data line shielding structure may be a routing line, a blanket layer, a mesh layer formed in one or more metal layers, and/or a data line covering another data line.Type: GrantFiled: May 25, 2023Date of Patent: April 23, 2024Assignee: Apple Inc.Inventors: Shinya Ono, Suhwan Moon, Dong-Gwang Ha, Jiaxi Hu, Hao-Lin Chiu, Kwang Soon Park, Hassan Edrees, Wen-I Hsieh, Jiun-Jye Chang, Chin-Wei Lin, Kyung Wook Kim
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Publication number: 20240117930Abstract: A hydrogen storage device includes a storage container having an accommodation space in an interior thereof, a first metal hydride material provided in the interior of the storage container and that stores hydrogen, and a second metal hydride material provided in the interior of the storage container and that stores the hydrogen at a pressure that is different from that of the first metal hydride material. An advantageous effect of restraining an excessive rise of a pressure of the storage container and enhancing safety and reliability may be obtained.Type: ApplicationFiled: March 10, 2023Publication date: April 11, 2024Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATIONInventors: Ji Hye Park, Won Jung Kim, Kyung Moon Lee, Dong Hoon Nam, Young Jin Cho, Byeong Soo Shin, Ji Hoon Lee, Suk Hoon Hong, Hoon Mo Park, Yong Doo Son
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Publication number: 20240117941Abstract: A hydrogen storage system is disclosed and includes a storage unit including a plurality of unit storage containers, in which metal hydride materials are respectively provided in an interior thereof and which are connected to each other in parallel, and a thermal fluid line defining a thermal fluid passage, which passes via the plurality of unit storage containers continuously and through which a thermal fluid flows for heating or cooling the unit storage containers, thereby enhancing a storage performance and an efficiency of the hydrogen.Type: ApplicationFiled: March 10, 2023Publication date: April 11, 2024Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATIONInventors: Ji Hye Park, Won Jung Kim, Kyung Moon Lee, Dong Hoon Nam, Young Jin Cho, Byeong Soo Shin, Ji Hoon Lee, Suk Hoon Hong, Hoon Mo Park, Yong Doo Son
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Patent number: 11256496Abstract: A method for application management and an electronic device therefor are provided. The electronic device includes a memory configured to store a first application, and a processor configured to obtain a request for installing a second application, compare a first identifier corresponding to the first application with a second identifier corresponding to the second application, if the first identifier is the same as the second identifier, compare first signature information corresponding to the first application with second signature information corresponding to the second application, if the first signature information is different from the second signature information, compare the first signature information with additional signature information corresponding to the second application, and if the first signature information is the same as the additional signature information, replace at least a portion of the first application by using at least a portion of the second application.Type: GrantFiled: June 8, 2020Date of Patent: February 22, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Myeong Jin Oh, Moon Kyung Kim, Kyung Moon Kim, Jae Young Lee
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Publication number: 20200301697Abstract: A method for application management and an electronic device therefor are provided. The electronic device includes a memory configured to store a first application, and a processor configured to obtain a request for installing a second application, compare a first identifier corresponding to the first application with a second identifier corresponding to the second application, if the first identifier is the same as the second identifier, compare first signature information corresponding to the first application with second signature information corresponding to the second application, if the first signature information is different from the second signature information, compare the first signature information with additional signature information corresponding to the second application, and if the first signature information is the same as the additional signature information, replace at least a portion of the first application by using at least a portion of the second application.Type: ApplicationFiled: June 8, 2020Publication date: September 24, 2020Inventors: Myeong Jin OH, Moon Kyung KIM, Kyung Moon KIM, Jae Young LEE
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Patent number: 10678527Abstract: A method for application management and an electronic device therefor are provided. The electronic device includes a memory configured to store a first application, and a processor configured to obtain a request for installing a second application, compare a first identifier corresponding to the first application with a second identifier corresponding to the second application, if the first identifier is the same as the second identifier, compare first signature information corresponding to the first application with second signature information corresponding to the second application, if the first signature information is different from the second signature information, compare the first signature information with additional signature information corresponding to the second application, and if the first signature information is the same as the additional signature information, replace at least a portion of the first application by using at least a portion of the second application.Type: GrantFiled: October 21, 2016Date of Patent: June 9, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Myeong Jin Oh, Moon Kyung Kim, Kyung Moon Kim, Jae Young Lee
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Patent number: 10109587Abstract: An integrated circuit packaging system, and a method of manufacture thereof, including: a substrate including: a first trace layer, an encapsulation on the first trace layer, the first trace layer having a surface exposed from the encapsulation with a rough texture characteristic of removal of a conductive carrier coating, a second trace layer on the encapsulation and over the first trace layer, the second trace layer connected to the first trace layer; and an integrated circuit die attached to the substrate.Type: GrantFiled: August 2, 2016Date of Patent: October 23, 2018Assignee: STATS ChipPAC Pte. Ltd.Inventors: Dao Nguyen Phu Cuong, Bartholomew Liao Chung Foh, Byung Tai Do, Kyung Moon Kim, Jeffrey David Punzalan, SeungYong Chai, Soo Won Lee, Kwok Keung Szeto, KyungOe Kim
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Patent number: 9865554Abstract: An integrated circuit packaging system and method of manufacture thereof including: providing a substrate; forming contact pads on top of the substrate; forming a protection layer on top of the contact pads and the substrate; exposing the contact pads from the protection layer; printing under bump metallization (UBM) layers over the exposed contact pads extended over the protection layer with conductive inks; and forming bumps on top of the under bump metallization layers. It also including: printing an adhesion layer using conductive ink, wherein the adhesion layer comprises interconnected adhesion layer pads; forming additional under bump metallization (UBM) layers and bumps on top of the adhesion layer pads utilizing an electro-deposition process; and removing connections among the interconnected adhesion layer pads.Type: GrantFiled: November 30, 2015Date of Patent: January 9, 2018Assignee: STATS ChipPAC Ptc. Ltd.Inventors: Il Kwon Shim, Kyung Moon Kim, HeeJo Chi, JunMo Koo, Bartholomew Liao Chung Foh, Zigmund Ramirez Camacho
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Patent number: 9748157Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a base substrate having a bottom pad; an integrated circuit device mounted on the base substrate; an interposer having a package interconnect mounted on the base substrate, the package interconnect includes an underside base portion having an irregular surface characteristic of a coining process; and an encapsulation between the interposer and the base substrate.Type: GrantFiled: May 29, 2013Date of Patent: August 29, 2017Assignee: STATS ChipPAC Pte. Ltd.Inventors: HeeJo Chi, HanGil Shin, NamJu Cho, Kyung Moon Kim
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Publication number: 20170115981Abstract: A method for application management and an electronic device therefor are provided. The electronic device includes a memory configured to store a first application, and a processor configured to obtain a request for installing a second application, compare a first identifier corresponding to the first application with a second identifier corresponding to the second application, if the first identifier is the same as the second identifier, compare first signature information corresponding to the first application with second signature information corresponding to the second application, if the first signature information is different from the second signature information, compare the first signature information with additional signature information corresponding to the second application, and if the first signature information is the same as the additional signature information, replace at least a portion of the first application by using at least a portion of the second application.Type: ApplicationFiled: October 21, 2016Publication date: April 27, 2017Inventors: Myeong Jin OH, Moon Kyung KIM, Kyung Moon KIM, Jae Young LEE
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Patent number: 9412624Abstract: An integrated circuit packaging system, and a method of manufacture thereof, including: a substrate including: a first trace layer, an encapsulation on the first trace layer, the first trace layer having a surface exposed from the encapsulation with a rough texture characteristic of removal of a conductive carrier coating, a second trace layer on the encapsulation and over the first trace layer, the second trace layer connected to the first trace layer; and an integrated circuit die attached to the substrate.Type: GrantFiled: June 26, 2014Date of Patent: August 9, 2016Assignee: STATS ChipPAC Pte. Ltd.Inventors: Dao Nguyen Phu Cuong, Bartholomew Liao Chung Foh, Byung Tai Do, Kyung Moon Kim, Jeffrey David Punzalan, SeungYong Chai, Soo Won Lee, Kwok Keung Szeto, KyungOe Kim
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Patent number: 9312150Abstract: A method for forming metallurgical interconnections and polymer adhesion of a flip chip to a substrate includes providing a chip having a set of bumps formed on a bump side thereof and a substrate having a set of interconnect points on a metallization thereon, providing a measured quantity of a polymer adhesive in a middle region of the chip on the bump side, aligning the chip with the substrate so that the set of bumps aligns with the set of interconnect points, pressing the chip and the substrate toward one another so that a portion of the polymer adhesive contacts the substrate and the bumps contact the interconnect points, and heating the bumps to a temperature sufficiently high to form a metallurgical connection between the bumps and the interconnect points.Type: GrantFiled: October 7, 2011Date of Patent: April 12, 2016Assignee: STATS ChipPAC, Ltd.Inventors: Nazir Ahmad, Young-Do Kweon, Samuel Tam, Kyung-Moon Kim, Rajendra D. Pendse
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Publication number: 20160099222Abstract: An integrated circuit packaging system and method of manufacture thereof including: providing a substrate; forming contact pads on top of the substrate; forming a protection layer on top of the contact pads and the substrate; exposing the contact pads from the protection layer; printing under bump metallization (UBM) layers over the exposed contact pads extended over the protection layer with conductive inks; and forming bumps on top of the under bump metallization layers. It also including: printing an adhesion layer using conductive ink, wherein the adhesion layer comprises interconnected adhesion layer pads; forming additional under bump metallization (UBM) layers and bumps on top of the adhesion layer pads utilizing an electro-deposition process; and removing connections among the interconnected adhesion layer pads.Type: ApplicationFiled: November 30, 2015Publication date: April 7, 2016Inventors: Il Kwon Shim, Kyung Moon Kim, HeeJo Chi, JunMo Koo, Bartholomew Liao Chung Foh, Zigmund Ramirez Camacho
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Patent number: 9299650Abstract: An integrated circuit packaging system and method of manufacture thereof including: a base substrate; an integrated circuit die on the base substrate; vertical interconnects attached to the base substrate around the integrated circuit die; and a single metal layer interposer mounted on the vertical interconnects, the single metal layer interposer including: a routing pattern having interposer contacts and traces, and a dielectric layer on the interposer contacts and traces, a top surface of the interposer contacts coplanar with a top surface of the dielectric layer.Type: GrantFiled: September 25, 2013Date of Patent: March 29, 2016Assignee: STATS ChipPAC Ltd.Inventors: HeeJo Chi, HanGil Shin, NamJu Cho, Kyung Moon Kim
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Patent number: 9202793Abstract: An integrated circuit packaging system and method of manufacture thereof including: providing a substrate; forming contact pads on top of the substrate; forming a protection layer on top of the contact pads and the substrate; exposing the contact pads from the protection layer; printing under bump metallization (UBM) layers over the exposed contact pads extended over the protection layer with conductive inks; and forming bumps on top of the under bump metallization layers. It also including: printing an adhesion layer using conductive ink, wherein the adhesion layer comprises interconnected adhesion layer pads; forming additional under bump metallization (UBM) layers and bumps on top of the adhesion layer pads utilizing an electro-deposition process; and removing connections among the interconnected adhesion layer pads.Type: GrantFiled: December 26, 2013Date of Patent: December 1, 2015Assignee: STATS ChipPAC Ltd.Inventors: Il Kwon Shim, Kyung Moon Kim, HeeJo Chi, JunMo Koo, Bartholomew Liao, Zigmund Ramirez Camacho
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Patent number: 8951834Abstract: Methods of forming solder balls for semiconductor packages using film-assisted molding include providing a substrate, forming a plurality of solder balls on the substrate where each solder ball has an initial profile, and coupling a substantially planar film to the solder balls. As an encapsulation is deposited over the substrate and around the solder balls, the substantially planar film and the encapsulation, along with the molding process, can cause each solder ball to morph from its initial profile to a final profile, where the final profile is generally different from the initial profile.Type: GrantFiled: June 28, 2013Date of Patent: February 10, 2015Assignee: STATS ChipPAC Ltd.Inventors: Kyung Moon Kim, Il Kwon Shim, HeeJo Chi, HanGil Shin
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Patent number: 8604624Abstract: A flip chip interconnection system includes: providing a conductive lead coated with a protective coating; forming a groove through the protective coating to the conductive lead for controlling solder position on a portion of the conductive lead; and attaching a flip chip having a solderable conductive interconnect to the portion of the conductive lead.Type: GrantFiled: March 19, 2008Date of Patent: December 10, 2013Assignee: Stats Chippac Ltd.Inventors: Oh Han Kim, Kyung Moon Kim
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Publication number: 20130113093Abstract: A method for forming metallurgical interconnections and polymer adhesion of a flip chip to a substrate includes providing a chip having a set of bumps formed on a bump side thereof and a substrate having a set of interconnect points on a metallization thereon, providing a measured quantity of a polymer adhesive in a middle region of the chip on the bump side, aligning the chip with the substrate so that the set of bumps aligns with the set of interconnect points, pressing the chip and the substrate toward one another so that a portion of the polymer adhesive contacts the substrate and the bumps contact the interconnect points, and heating the bumps to a temperature sufficiently high to form a metallurgical connection between the bumps and the interconnect points.Type: ApplicationFiled: October 7, 2011Publication date: May 9, 2013Applicant: STATS CHIPPAC, LTD.Inventors: Nazir Ahmad, Young-Do Kweon, Samuel Tam, Kyung-Moon Kim, Rajendra D. Pendse
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Publication number: 20120217635Abstract: A method of making a semiconductor device includes providing a substrate and forming a conductive layer on the substrate. The conductive layer includes a first metal. A semiconductor die is provided. A bump is formed on the semiconductor die. The bump includes a second metal. The semiconductor die is positioned proximate to the substrate to contact the bump to the conductive layer and form a bonding interface. The bump and the conductive layer are metallurgically reacted at a melting point of the first metal to dissolve a portion of the second metal from an end of the bump. The bonding interface is heated to the melting point of the first metal for a time sufficient to melt a portion of the first metal from the conductive layer. A width of the conductive layer is no greater than a width of the bump.Type: ApplicationFiled: September 26, 2011Publication date: August 30, 2012Applicant: STATS CHIPPAC, LTD.Inventors: Nazir Ahmad, Young-Do Kwon, Samuel Tam, Kyung-Moon Kim, Rajendra D. Pendse