Abstract: A semiconductor integrated circuit device comprising: a substrate; a buried layer disposed on one side of the substrate; a well including a semiconductor region disposed on one side of the buried layer; and a Schottky diode portion disposed on one side of the well, wherein the Schottky diode portion comprises an anode, a guard ring electrically connected with the anode, and a poly field plate electrically connected with the anode and the guard ring, and the guard ring comprises at least one slit configured to block a flow of current.

Abstract: A FOUP comprises: an external server; and a substrate processing device for performing substrate processing and transmitting integrated management data to the external server. The substrate processing device comprises: FOUPs for accommodating a plurality of substrates; load ports to which the FOUPs are detachably coupled; a process chamber in which substrate processing is performed; an EFEM, which is provided between the process chamber and the load ports, and has an end effector for getting, into the process chamber, the substrates accommodated in the FOUPs or putting, into the FOUPs, the substrates for which processing is completed in the process chamber; and a control unit for transmitting, if the FOUPs are loaded in the load ports, moving path data of the end effector to the external server when the end effector enters into or retreats from the FOUPs.

Abstract: The present invention relates to a position determination apparatus for a robot detection laser sensor system in front-opening unified pods (FOUPs), including: an external server; and a wafer processing device for performing processing for wafers and transmitting integration management data to the external server, wherein the wafer processing device may include: the FOUPs configured to accommodate the wafers therein; loadports to which the FOUPs are detachably coupled; processing chambers in which the processing for the wafers are performed; and an equipment front end module (EFEM) disposed between the processing chambers and the loadports and having an end-effector adapted to get the wafers out of the FOUPs into the processing chambers or put the wafers finished in processing in the processing chambers into the FOUPs.

Abstract: A semiconductor device includes a substrate, a gate electrode disposed on an upper surface of the substrate, a source region disposed on a first side of the gate electrode, a drain region disposed on a second side of the gate electrode opposite to the first side of the gate electrode in a horizontal direction, and an insulating structure at least partially buried inside the substrate on the substrate. The insulating structure includes a first portion disposed between the substrate and the gate electrode, and a second portion in contact with the drain region. An uppermost surface of the second portion of the insulating structure is lower than an uppermost surface of the first portion of the insulating structure. At least a part of the gate electrode is disposed on the uppermost surface of the second portion of the insulating structure.

Abstract: A semiconductor device includes a field oxide layer formed on a substrate, a gate insulating layer formed on a surface portion of the substrate adjacent to one side of the field oxide layer, a gate electrode formed on the gate insulating layer and a portion of the field oxide layer, a source region formed in a surface portion of the substrate adjacent to one side of the gate electrode, and a drain region formed in a surface portion of the substrate adjacent to another side of the field oxide layer. A surface portion of the substrate on which the field oxide layer is formed is convex upward.

Abstract: Provided are an end effect measuring module and an end effect monitoring apparatus using the same. The end effect measuring module is installed at through holes formed between an Equipment Front End Module (EFEM) equipped with an end effector and a semiconductor processing apparatus for processing a wafer and measuring the position according to the movement path of a target passing the through holes. The measurement target is the end effector, and a sensing unit measures whether or not the end effector is shifted and changed in direction. A light receiving unit of the sensing unit outputs an electrical signal that is higher or lower than a reference value in response to shifting of the end effector, or outputs an electrical signal increasing or decreasing along a time axis in response to a directional change of the end effector.

Abstract: A semiconductor device includes a substrate, a gate electrode disposed on an upper surface of the substrate, a source region disposed on a first side of the gate electrode, a drain region disposed on a second side of the gate electrode opposite to the first side of the gate electrode in a horizontal direction, and an insulating structure at least partially buried inside the substrate on the substrate. The insulating structure includes a first portion disposed between the substrate and the gate electrode, and a second portion in contact with the drain region. An uppermost surface of the second portion of the insulating structure is lower than an uppermost surface of the first portion of the insulating structure. At least a part of the gate electrode is disposed on the uppermost surface of the second portion of the insulating structure.

Abstract: Provided are an end effect measuring module and an end effect monitoring apparatus using the same. The end effect measuring module is installed at through holes formed between an Equipment Front End Module (EFEM) equipped with an end effector and a semiconductor processing apparatus for processing a wafer and measuring the position according to the movement path of a target passing the through holes. The measurement target is the end effector, and a sensing unit measures whether or not the end effector is shifted and changed in direction. A light receiving unit of the sensing unit outputs an electrical signal that is higher or lower than a reference value in response to shifting of the end effector, or outputs an electrical signal increasing or decreasing along a time axis in response to a directional change of the end effector.

Abstract: A power device includes a drift layer of a second conductivity type located on a semiconductor layer of a first conductivity type, a first source region of the second conductivity type and a second source region of the second conductivity type, located on the drift layer to be apart from each other, and a gate electrode on the drift layer between the first and second source regions with a gate insulating layer between the gate electrode and the drift layer, wherein the gate electrode includes a first gate electrode and a second gate electrode adjacent to the first source region and the second source region, respectively, and a third gate electrode between the first and second gate electrodes, wherein the third gate electrode is floated or grounded.

Abstract: A power device includes a drift layer of a second conductivity type located on a semiconductor layer of a first conductivity type, a first source region of the second conductivity type and a second source region of the second conductivity type, located on the drift layer to be apart from each other, and a gate electrode on the drift layer between the first and second source regions with a gate insulating layer between the gate electrode and the drift layer, wherein the gate electrode includes a first gate electrode and a second gate electrode adjacent to the first source region and the second source region, respectively, and a third gate electrode between the first and second gate electrodes, wherein the third gate electrode is floated or grounded.

Abstract: A semiconductor device, including a substrate; a first conductive type well and a second conductive type body region at an upper portion of the substrate; a field plate on the first conductive type well, the field plate including a semiconductor material or an insulative nitride; and a gate electrode extending in a lateral direction on the substrate from a lateral portion of the second conductive type body region to a lateral portion of the first conductive type well, the gate electrode overlapping the field plate.

Abstract: A vertical junction field-effect transistor in a CMOS base-technology. The vertical junction field-effect transistor includes a semiconductor substrate having a source region and a drain region, a main-channel region formed between the source region and the drain region, a well region formed on the main-channel region between the source region and the drain region, vertical pinch-off regions formed at both source and drain ends or only on the source-end of the well region on the main-channel region in the source region and the drain region respectively, a source contact on the vertical pinch-off region in the source region, a drain contact on the vertical pinch-off region in the drain region, a gate contact on the well region between the source contact and the drain contact and shallow trench isolations formed on the well region.

Abstract: A vertical junction field-effect transistor in a CMOS base-technology. The vertical junction field-effect transistor includes a semiconductor substrate having a source region and a drain region, a main-channel region formed between the source region and the drain region, a well region formed on the main-channel region between the source region and the drain region, vertical pinch-off regions formed at both source and drain ends or only on the source-end of the well region on the main-channel region in the source region and the drain region respectively, a source contact on the vertical pinch-off region in the source region, a drain contact on the vertical pinch-off region in the drain region, a gate contact on the well region between the source contact and the drain contact and shallow trench isolations formed on the well region.

Abstract: The present invention relates to semiconductor technologies, and more particularly to a bipolar junction transistor (BJT) in a CMOS base technology and methods of forming the same. The BJT includes a semiconductor substrate having an emitter region, a base having a first contact, and a collector having a second contact and a well plug; a first silicide film on the first contact; a second silicide film on the second contact; a first silicide blocking layer on or over the semiconductor substrate between the first and second silicide films, and a second silicide blocking layer on the semiconductor substrate between the first silicide film and the emitter region.

Abstract: A method of manufacturing a recessed gate transistor includes forming a hard mask pattern over a substrate; and then forming a trench in the substrate by performing an etching process using the hard mask pattern as an etch mask; and then performing a pullback-etching process on the hard mask pattern to expose a source region in the substrate; and then forming a gate silicon layer in the trench and over the substrate including the hard mask pattern after performing the pullback-etching process; and then performing an etch-back process on the gate silicon layer to expose the hard mask pattern such that the uppermost surface of the gate silicon layer is below the uppermost surface of the hard mask pattern; and then removing the hard mask pattern; and then simultaneously etching the gate silicon layer and the exposed portion of the substrate.

Abstract: A method of manufacturing a recessed gate transistor includes forming a hard mask pattern over a substrate; and then forming a trench in the substrate by performing an etching process using the hard mask pattern as an etch mask; and then performing a pullback-etching process on the hard mask pattern to expose a source region in the substrate; and then forming a gate silicon layer in the trench and over the substrate including the hard mask pattern after performing the pullback-etching process; and then performing an etch-back process on the gate silicon layer to expose the hard mask pattern such that the uppermost surface of the gate silicon layer is below the uppermost surface of the hard mask pattern; and then removing the hard mask pattern; and then simultaneously etching the gate silicon layer and the exposed portion of the substrate.

Abstract: Disclosed herein is a wafer carrier locking device. The wafer carrier locking device includes a wafer carrier seated thereon a plurality of wafers. A main equipment executes a semiconductor manufacturing process, which is a wafer cleaning process, a wafer etching process, etc., when the wafers seated on the wafer carrier are fed to the main equipment by a multi-joint robot. An auxiliary equipment includes a carrier sensor to detect a seated state of the wafer carrier relative to a base member, a wafer sensor to detect a number and positions of the wafers seated on the wafer carrier, when the wafer carrier is seated on the base member, and the base member having a plate shape. In this case, a plurality of positioning blocks are provided at predetermined positions of the base member to allow the wafer carrier to be seated at a desired position on the base member.