Abstract: The invention relates to a solar photovoltaic array module design, which constitutes three steps of optical concentrations of photovoltaic electric power generation systems. A compound parabolic concentrator (CPC) is mounted under a first optical concentrating fresnel lens that concentrates the intensity of sunlight to five times above normal level. Then the focused sunlight is further concentrated twenty times by the second optical concentrator CPC. The high mirror quality of CPC allows 98% of the reflected rays to be focused at the bottom of the CPC. At this point, the intensified sunlight passes through a third optical concentrator glass lens, which with anti-reflection coating on the top of the glass lens' surface, incident on the multi-junction solar cell accomplish the third optical concentration for the photovoltaic electric energy conversion.

Abstract: A stationary solar photovoltaic array module design, which constitutes four steps of optical concentrations of photovoltaic electric power generation systems. A compound parabolic concentrator (CPC) is mounted under a first and second optical concentrating fresnel lenses that concentrates the intensity of sunlight. Then the focused sunlight is further concentrated twenty times by the third optical concentrator CPC. The high mirror quality of CPC allows 98% of the reflected rays to be focused at the bottom of the CPC. At this point, the intensified sunlight is homogenized as it passes through a fourth optical concentrator glass lens, which with anti-reflection coating on the top of the glass lens' surface, incident on the multi-junction solar cell accomplish the fourth optical concentration for the photovoltaic electric energy conversion.

Abstract: The present invention discloses a method for forming a DRAM capacitor that has improved charge capacitance which can be carried out by first depositing an oxide layer on a semiconducting substrate, forming an uneven surface on the oxide layer, forming a capacitor node in the oxide layer to expose the substrate, depositing a polysilicon layer on top of the oxide layer and in the node such that the uneven surface on the oxide layer is substantially reproduced in a top surface of the polysilicon layer, depositing a dielectric layer and a second polysilicon layer sequentially on top of the first polysilicon layer to reproduce the uneven surface on the oxide layer, and then defining the DRAM capacitor.

Abstract: The present invention discloses a method for forming a DRAM capacitor that has improved charge capacity and a DRAM capacitor formed by such method. The method can be carried out by first depositing an oxide layer on a lower polysilicon electrode layer on a semiconductor structure, then polishing the top surface of the oxide layer to form an uneven surface which provides increased surface area, and then anisotropically etching away the oxide layer while reproducing the uneven surface of the oxide layer onto the lower polysilicon electrode layer such that an increased charge capacity can be realized. The anisotropic etch chemistry should be selected such that the etchant etches away both the oxide layer and the polysilicon layer, and preferably, the etchant should have a higher selectivity toward polysilicon and a lower selectivity toward oxide such that the oxide layer can be completely removed while only a portion of the polysilicon layer is removed to form the uneven surface.

Abstract: The present invention discloses a method for increasing capacitance in DRAM capacitors by the operating steps of first providing a cavity in a semiconductor substrate, then depositing a first polysilicon layer in the cavity, and a metal layer on top of the polysilicon layer to form a silicide layer. The semiconductor substrate is then heat treated in a rapid thermal processing method so that the metal silicide layer forms an island structure on top of the first polysilicon layer. The first polysilicon layer can then be isotropically etched by using the metal silicide island structure as a mask to form an island structure in the first polysilicon layer. Additional dielectric layer and polysilicon layers are then deposited to form the insulating layer and the upper electrode for the capacitor. The increased surface area, i.e., approximately two times, of the lower electrode polysilicon layer greatly increases its storage area for the capacitor and therefore greatly improves its capacitance.