Abstract: Processing signals is disclosed. A method includes receiving a signal transmission with a nb/mb encoding scheme that maps n-bit words to m-bit symbols. In this scheme, m>n. The method further includes, for a first payload data word in the transmission, determining that the first payload data word corresponds to a valid payload data word, and as a result, assigning a first reliability metric to bits in the first payload data word. The method further includes for a second payload data word in the transmission, determining that the second payload data word does not correspond to a valid payload data word, and as a result, assigning a second reliability metric to bits in the second payload data word. The method further includes performing signal decoding using the assigned reliability metrics.

Abstract: Processing signals is disclosed. A method includes receiving a signal transmission with a nb/mb encoding scheme that maps n-bit words to m-bit symbols. In this scheme, m>n. The method further includes, for a first payload data word in the transmission, determining that the first payload data word corresponds to a valid payload data word, and as a result, assigning a first reliability metric to bits in the first payload data word. The method further includes for a second payload data word in the transmission, determining that the second payload data word does not correspond to a valid payload data word, and as a result, assigning a second reliability metric to bits in the second payload data word. The method further includes performing signal decoding using the assigned reliability metrics.

Abstract: Clock recovery from a serial data signal involves using a serializer/deserializer (SERDES) to produce a clock signal which periodically alternates between high and low output clock values. These high and low clock values are generated by outputting for each clock period a series of N digital bits including a plurality of low-level bits to form each low output clock value and a plurality of high-level bits to form each high output clock value. A sync pulse obtained from a sync word present in each frame of the serial data signal is used to periodically determine a frequency error of the clock signal. The frequency error is used as a basis to change a phase of the adjusted clock signal responsive to the frequency error.

Abstract: Systems and methods for synchronize word correlation. The methods comprise: obtaining first values that each indicate a likelihood or probability that a respective timeslot in a symbol timing window of a carrier wave is meant or expected to include energy; multiplying, by the correlator, the first values respectively by correlation coefficients to produce a plurality of products (wherein at least one of the correlation coefficients comprises a negative coefficient value); generating a correlation value by combining the products together; determining whether a synchronization word has been detected with a given amount of likelihood based on the correlation value; and causing symbol timing synchronization at a receiver when a determination is made that the synchronization word has been detected with the given amount of likelihood based on the correlation value.

Abstract: Systems and methods for synchronize word correlation. The methods comprise: obtaining first values that each indicate a likelihood or probability that a respective timeslot in a symbol timing window of a carrier wave is meant or expected to include energy; multiplying, by the correlator, the first values respectively by correlation coefficients to produce a plurality of products (wherein at least one of the correlation coefficients comprises a negative coefficient value); generating a correlation value by combining the products together; determining whether a synchronization word has been detected with a given amount of likelihood based on the correlation value; and causing symbol timing synchronization at a receiver when a determination is made that the synchronization word has been detected with the given amount of likelihood based on the correlation value.

Abstract: Clock recovery from a serial data signal involves using a serializer/deserializer (SERDES) to produce a clock signal which periodically alternates between high and low output clock values. These high and low clock values are generated by outputting for each clock period a series of N digital bits including a plurality of low-level bits to form each low output clock value and a plurality of high-level bits to form each high output clock value. A sync pulse obtained from a sync word present in each frame of the serial data signal is used to periodically determine a frequency error of the clock signal. The frequency error is used as a basis to change a phase of the adjusted clock signal responsive to the frequency error.

Abstract: Clock recovery from a serial data signal involves using a serializer/deserializer (SERDES) to produce a clock signal which periodically alternates between high and low output clock values. These high and low clock values are generated by outputting for each clock period a series of N digital bits including a plurality of low-level bits to form each low output clock value and a plurality of high-level bits to form each high output clock value. A sync pulse obtained from a sync word present in each frame of the serial data signal is used to periodically determine a frequency error of the clock signal. The frequency error is used as a basis to change a phase of the adjusted clock signal responsive to the frequency error.

Abstract: Systems and methods for operating a communication device. The methods comprise: receiving a carrier signal modulated with a modulation signal comprising a symbol conveyed in a symbol timing window; determining an energy value for each timeslot in the symbol timing window; combining the energy values to determine a combined energy value for each bit of the symbol in a manner in which the combined energy value is penalized if more than one timeslot of the symbol timing window comprises energy contained in the carrier signal; and generating a soft value for each bit of the sequence of bits by combining the combined energy value with a weight value, where the weight value is selected from a plurality of weight values based on a number of timeslots in the symbol timing window which comprises energy contained in the carrier signal.

Abstract: A return-to-zero control signal for controlling a modulator can be generated from two separate streams. A first data stream can include a pulse for each logical one that appears in an input data stream, while a second data stream can include a pulse for each logical zero that appears in the input data stream. The first and second data streams can be combined in a manner that yields the return-to-zero control signal. The first and second data streams can be generated in digital circuitry, such as an FPGA, to minimize the analog path for generating the return-to-zero control signal.