Abstract: A method for processing cells at a user-network interface with automatic identification of virtual circuit identifiers and a testing function is provided. The method includes distinguishing the source of the cell. When the cell is from a first source, the method tests the cell against at least one selected criteria. When at least one test determines the cell is invalid, the cell is marked. When the tests determine that the cell is valid, the method translates a virtual circuit identifier to a default setting and forwards the cell to a queue for further processing.

Abstract: A device for determining speeds of a digital signal in a serial transmission line. The device comprises a first and second counter and a logic circuit. The first counter is adapted to count the duration of a first pulse in a first byte of the digital signal in the transmission line. The second counter is adapted to count the duration of a second pulse in the first byte. The logic circuit is coupled to the first and second counters. The logic circuit is adapted to compare the smallest duration of the first and second pulses with a plurality of pulse duration's of known baud rates to determine the baud rate of the digital signal in the transmission line.

Abstract: Testing an oscillator and other electronic devices on a circuit board. One method of the present invention comprises powering the oscillator. Providing test instructions to a microprocessor on the circuit board to place the microprocessor in a test mode. Receiving a clock signal from the oscillator at a multiplexer in a field programmable gate array. Receiving operating instructions at the multiplexer from the microprocessor. Multiplexing the clock signal to an external access port with the multiplexer in response to the operating instructions and measuring the frequency of the clock signal at the external access port.

Abstract: Testing of analog-to-digital and digital-to-analog converters formed in integrated circuits. In one embodiment, a method of testing an analog-to-digital (A/D) converter comprises applying an analog test signal of a first frequency to an input of the A/D converter. Sampling digital byte samples from an output of the A/D converter at a second sampling frequency and comparing select digital byte samples with each other. When the select digital byte samples match, storing a verify bit in a memory to verify the A/D converter is working. In another embodiment, a method of testing a digital-to-analog (D/A) comprises creating repeating digital byte samples with a logic circuit formed in the integrated circuit. Converting the repeating digital byte samples into an analog test signal with the D/A converter. Comparing the frequency of the analog test signal with the frequency of an expected analog signal to determine if the D/A converter is working.

Abstract: A method and system for performing simultaneous tests and avoiding task collisions using a hardware description language includes designating a timeslot for one or more of the simultaneous tests, associating the designated timeslot with one or more of the tasks to be performed in a test, determining if the designated timeslot is available before executing the tasks associated with timeslots and executing the tasks when the designated timeslots become available.

Abstract: Testing an oscillator and other electronic devices on a circuit board. One method of the present invention comprises powering the oscillator. Providing test instructions to a microprocessor on the circuit board to place the microprocessor in a test mode. Receiving a clock signal from the oscillator at a multiplexer in a field programmable gate array. Receiving operating instructions at the multiplexer from the microprocessor. Multiplexing the clock signal to an external access port with the multiplexer in response to the operating instructions and measuring the frequency of the clock signal at the external access port.

Abstract: Testing of analog-to-digital and digital-to-analog converters formed in integrated circuits. In one embodiment, a method of testing an analog-to-digital (A/D) converter comprises applying an analog test signal of a first frequency to an input of the A/D converter. Sampling digital byte samples from an output of the A/D converter at a second sampling frequency and comparing select digital byte samples with each other. When the select digital byte samples match, storing a verify bit in a memory to verify the A/D converter is working. In another embodiment, a method of testing a digital-to-analog (D/A) comprises creating repeating digital byte samples with a logic circuit formed in the integrated circuit. Converting the repeating digital byte samples into an analog test signal with the D/A converter. Comparing the frequency of the analog test signal with the frequency of an expected analog signal to determine if the D/A converter is working.

Abstract: A method for processing cells at a user-network interface with automatic identification of virtual circuit identifiers and a testing function is provided. The method includes distinguishing the source of the cell. When the cell is from a first source, the method tests the cell against at least one selected criteria. When at least one test determines the cell is invalid, the cell is marked. When the tests determine that the cell is valid, the method translates a virtual circuit identifier to a default setting and forwards the cell to a queue for further processing.

Abstract: A method and system for performing simultaneous tests and avoiding task collisions using a hardware description language includes designating a timeslot for one or more of the simultaneous tests, associating the designated timeslot with one or more of the tasks to be performed in a test, determining if the designated timeslot is available before executing the tasks associated with timeslots and executing the tasks when the designated timeslots become available.

Abstract: A device for determining speeds of a digital signal in a serial transmission line. The device comprises a first and second counter and a logic circuit. The first counter is adapted to count the duration of a first pulse in a first byte of the digital signal in the transmission line. The second counter is adapted to count the duration of a second pulse in the first byte. The logic circuit is coupled to the first and second counters. The logic circuit is adapted to compare the smallest duration of the first and second pulses with a plurality of pulse duration's of known baud rates to determine the baud rate of the digital signal in the transmission line.