Patents by Inventor L. James Hwang

L. James Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200371759
    Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion having High-Level Synthesis (HLS) kernels for implementation within programmable logic (PL) of the device, a first interface solution is generated that maps logical resources used by the software portion to hardware resources of an interface block coupling the DPE array and the PL. A connection graph specifying connectivity among the HLS kernels and nodes of the software portion to be implemented in the DPE array; and, a block diagram based on the connection graph and the HLS kernels are generated. The block diagram is synthesizable. An implementation flow is performed on the block diagram based on the first interface solution. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.
    Type: Application
    Filed: May 23, 2019
    Publication date: November 26, 2020
    Applicant: Xilinx, Inc.
    Inventors: Akella Sastry, Vinod K. Kathail, L. James Hwang, Shail Aditya Gupta, Vidhumouli Hunsigida, Siddarth Rele
  • Patent number: 10635769
    Abstract: Event tracing for a system-on-chip (SOC) may be implemented by instrumenting, using a computer, a design for the SOC with instrumentation program code that, responsive to execution by a processor of the SOC, generates software trace events. The design may be specified in a high level programming language. A circuit design specifying an accelerator circuit for a function of the design may be generated using the computer. The accelerator circuit is configured for implementation within programmable circuitry of the SOC. The circuit design may be instrumented to include trace circuitry using the computer. The trace circuitry may be configured to detect hardware trace events for operation of the accelerator circuit, receive the software trace events, and combine the hardware and software trace events into time synchronized trace data.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: April 28, 2020
    Assignee: Xilinx, Inc.
    Inventors: Samuel A. Skalicky, L. James Hwang, Vinod K. Kathail
  • Patent number: 9880966
    Abstract: Application-specific tailoring and reuse of a platform for a target integrated circuit may include determining, using a processor, a plurality of unused interfaces of the platform and determining, using the processor, connectivity of a circuit block to be coupled to the platform within the target integrated circuit. The method may include coupling, using the processor, the circuit block to the platform using an interface that is compatible with the circuit block and selected from the plurality of unused interfaces of the platform.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: January 30, 2018
    Assignee: XILINX, INC.
    Inventors: L. James Hwang, Vinod K. Kathail, Sundararajarao Mohan, Jorge E. Carrillo, Hua Sun
  • Patent number: 9805152
    Abstract: In an example implementation, a method is provided for compiling an HLL source file including function calls to one or more hardware accelerated functions. Function calls in the HLL source file to hardware accelerated functions are identified and grouped into a plurality of subsets for exclusive implementation in programmable logic resources. Sets of configuration data are generated for configuration of the programmable logic resources to implement hardware accelerated functions for the respective subsets of function calls. An interface manager is generated and the identified function calls are replaced with interface code configured to communicate with the interface manager. The interface manager manages configuration of the programmable logic resources to switch between the sets of configuration data to implement hardware accelerated functions for different ones of the subsets.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: October 31, 2017
    Assignee: XILINX, INC.
    Inventors: Jorge E. Carrillo, Vinod K. Kathail, L. James Hwang, Sundararajarao Mohan, Hua Sun
  • Patent number: 9652570
    Abstract: Implementing a system-on-chip (SOC) design specified as a high level programming language (HLL) application may include querying, using a computer, a platform description to determine an available interface of a platform for a target integrated circuit and generating, using the computer, hardware for a function of the HLL application marked for hardware acceleration and hardware coupling the marked function with the available interface of the platform. Implementing the SOC design may also include modifying, using the computer, the HLL application with program code configured to access the generated hardware for the marked function and building, using the computer, the hardware and the software of the SOC design.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: May 16, 2017
    Assignee: XILINX, INC.
    Inventors: Vinod K. Kathail, L. James Hwang, Sundararajarao Mohan, Jorge E. Carrillo, Hua Sun, Tom Shui, Yogesh L. Chobe
  • Patent number: 9223921
    Abstract: In an example implementation, a method is provided for compiling an HLL source file. The HLL source file checked for function calls to a set of hardware-accelerated functions having hardware implementations specified in a hardware library. For each HLL function call to a hardware-accelerated function, a circuit design is retrieved from the hardware library. The circuit design specifies a hardware implementation of the hardware-accelerated function. HLL interface code configured to communicate with the hardware implementation of the hardware-accelerated function is also generated. The HLL function call to the hardware-accelerated function in the HLL source file is replaced with the generated interface code. The HLL source file is compiled to generate a program executable on a processor of a programmable IC. Configuration data is generated that implements the retrieved circuit designs on the programmable circuitry of the programmable IC.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: December 29, 2015
    Assignee: XILINX, INC.
    Inventors: Jorge E. Carrillo, L. James Hwang, Hua Sun, Sundararajarao Mohan, Vinod K. Kathail
  • Patent number: 9147024
    Abstract: Hardware and software co-synthesis performance estimation includes, for a design specified in a high level programming language and having a processor executable partition and a partition selected for hardware acceleration, estimating hardware latency for a hardware accelerator implementation of the selected partition, scheduling the selected partition using the hardware latency generating hardware partition latency information, and compiling an instrumented version of the design using a processor. The instrumented and compiled version of the design is executed generating software latency information. A design performance for the design is determined through combining the hardware partition latency information with the software latency information.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: September 29, 2015
    Assignee: XILINX, INC.
    Inventors: Vinod K. Kathail, Hua Sun, Sundararajarao Mohan, L. James Hwang, Yogesh L. Chobe
  • Patent number: 8868396
    Abstract: A method and apparatus for verifying and debugging a circuit design module of a high level programming system is disclosed herein. A circuit design created in a high level programming environment must undergo a number of transformations as it is compiled into a form that can be realized in hardware. At each transformative step, the behavior of the circuit must be verified with a simulation model and debugged if the transformation has changed the behavior of the circuit. The claimed invention presents a novel approach for verifying and debugging between different simulation models and achieves an advance in the art by utilizing the modularized structure of a high-level circuit design to systematically identify simulation mismatches among different simulation models and determine which portions of the circuit design are responsible for the discrepancy.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: October 21, 2014
    Assignee: Xilinx, Inc.
    Inventors: Nabeel Shirazi, L. James Hwang, Chi Bun Chan, Hem C. Neema, Kumar Deepak
  • Patent number: 8775986
    Abstract: A method is provided for synthesizing an HLL program. For one or more variables to observe and/or control in a function of the HLL program, a first code segment is added to the function in the HLL program. For each of the one or more variables a respective second code segment is also added to the HLL program. In response to encountering the first code segment during synthesis of the HLL program, a memory is instantiated in a synthesized design. In response to encountering the second code segment during synthesis of the HLL program, a respective interface circuit is instantiated in the synthesized design. Each interface circuit is configured to replicate a state of the corresponding variable in the memory during operation of the synthesized design. A table is generated that maps names of the one or more variables to respective memory addresses in the memory.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: July 8, 2014
    Assignee: Xilinx, Inc.
    Inventors: Sundararajarao Mohan, L. James Hwang
  • Patent number: 8762916
    Abstract: A method of automatically developing a data transfer network includes determining, using a processor, a plurality of data transfers of a function of a circuit design marked for hardware acceleration within a target integrated circuit. The circuit design is specified in a high level programming language, and at least one other function of the circuit design remains executable by a microprocessor of the target integrated circuit. Each of the plurality of data transfers is characterized. Each of the plurality of data transfers is correlated with resources of the target integrated circuit. A programmatic description of a data transfer network is generated for the circuit design. The data transfer network connects the hardware accelerator and the microprocessor according to the characterizing and the correlating.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: June 24, 2014
    Assignee: Xilinx, Inc.
    Inventors: Vinod K. Kathail, L. James Hwang, Sundararajarao Mohan, Hua Sun
  • Patent number: 8024678
    Abstract: An interface to a dynamically configurable arithmetic unit can include data alignment modules, where each data alignment module receives input variables being associated with one or more arithmetic expressions. The interface can include multiplexers coupled to the data alignment modules, wherein a data alignment module has outputs coupled to a first multiplexer. The first multiplexer can have a selection line and an output coupled to an input port of the dynamically configurable arithmetic unit. The interface can include a second multiplexer having input instructions and the selection line, where each instruction is associated with one of the arithmetic expressions and has an operation to be performed by the dynamically configurable arithmetic unit. The second multiplexer is configurable to provide selected ones of the input instructions to the dynamically configurable arithmetic unit through an output of the second multiplexer responsive to the selection line.
    Type: Grant
    Filed: April 1, 2009
    Date of Patent: September 20, 2011
    Assignee: Xilinx, Inc.
    Inventors: Bradley L. Taylor, Arvind Sundararajan, Shay Ping Seng, L. James Hwang
  • Patent number: 7934185
    Abstract: A method of modeling a design in a high level modeling system that supports unidirectional data flow, may comprise identifying a bus-block to represent a connectivity of a bi-directional bus in an system. The bus-block may be represented in serial relationship with the bus. Taps may interface the bus via the bus-block. During simulation, the bus-block emulates behavior of a tri-state buffer in series with an input line for the tap interface. During synthesis, pairs of unidirectional input and output lines of opposite data-routing orientation, which may emulate bus ports to the bus-block, may be collapsed to a single bus port. The synthesis may further generate a netlist that may dispose a tri-state buffer between a tap input and the bus. The netlist may also represent layout of the tri-state buffer for driving an output of the tap.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: April 26, 2011
    Assignee: Xilinx, Inc.
    Inventors: Jonathan B. Ballagh, Roger Brent Milne, Jeffrey D. Stroomer, L. James Hwang, Nabeel Shirazi
  • Patent number: 7895584
    Abstract: Method and apparatus for translating a first program in a dynamically-typed language to a program in a hardware description language. From the dynamically-typed-language first program, a second program in single static assignment format is generated. For cases where a variable is assigned different data types at different places in the program, the assignments of the different data types are resolved for the variable. The second program is then translated to a program in the hardware description language.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: February 22, 2011
    Assignee: Xilinx, Inc.
    Inventors: Haibing Ma, L. James Hwang, Jeffrey D. Stroomer, Roger B. Milne
  • Patent number: 7739092
    Abstract: A method of resetting a programmable logic device (PLD) for use with hardware co-simulation can include loading a full bitstream into the PLD. The full bitstream can program the PLD with a circuit design to be used with a first simulation. The method further can include loading a partial bitstream into the PLD thereby resetting at least one component of the circuit design that does not have a reset function such that the circuit design is initialized for use in a subsequent simulation.
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: June 15, 2010
    Assignee: Xilinx, Inc.
    Inventors: Jonathan B. Ballagh, L. James Hwang, Roger B. Milne, Kevin Marc Neilson, Nabeel Shirazi
  • Patent number: 7684968
    Abstract: Generating a high-level, bit-accurate and cycle-accurate simulation model. The various embodiments generate the simulation model from a functional description of a module and an HDL description of the module. The functional description may be un-timed and specified in a high-level language. The HDL description is realizable in hardware. The simulation model is created by obtaining the control specification from the HDL description and combining the control specification with the data path description from functional description.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: March 23, 2010
    Assignee: Xilinx, Inc.
    Inventors: Gabor Szedo, Singh Vinay Jitendra, L. James Hwang
  • Patent number: 7523434
    Abstract: An exemplary embodiment includes a method that receives a plurality of mathematical expressions having a plurality of input variables. The mathematical expressions can then be parsed, checked for proper syntax and one or more abstract syntax trees can be formed. Next, the input variables are then assigned to input ports of the dynamically configurable arithmetic unit. Then using the parsed mathematical expressions with the assigned input ports, a list of operations to be performed by the dynamically configurable arithmetic unit are determined. And lastly, an interface to the dynamically configurable arithmetic unit is generated using in part the variable-to-input port assignments and the list of operations.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: April 21, 2009
    Assignee: Xilinx, Inc.
    Inventors: Bradley L. Taylor, Arvind Sundararajan, Shay Ping Seng, L. James Hwang
  • Patent number: 7509614
    Abstract: The invention provides an interface that can facilitate integration of user specific proprietary cores and commercially available cores during customization of an FPGA-based SoC. A selected hardware or software system component used for customizing the FPGA-based SoC can be configured using parameters that can be automatically propagated and used to configure peer system components. During configuration of the peer system components, other parameters used to configure those peer system components can also be propagated and used to configure other system components during customization of the FPGA-based SoC.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: March 24, 2009
    Assignee: XILINX, Inc.
    Inventors: L. James Hwang, Reno L. Sanchez
  • Patent number: 7478030
    Abstract: Method and apparatus for clock stabilization detection for hardware simulation is described. More particularly, a lock signal is obtained, for example from a digital clock module. A least common multiple (LCM) clock signal is generated, for example from a clock module. A control signal is generated at least partially responsive to the LCM clock signal and the lock signal. The control signal may be generated from a state machine and applied to select circuitry, where the control signal is used to mask application of the output clock signal responsive to the control signal.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: January 13, 2009
    Assignee: Xilinx, Inc.
    Inventors: Jonathan B. Ballagh, Roger B. Milne, Jeffrey D. Stroomer, L. James Hwang, Nabeel Shirazi
  • Patent number: 7437280
    Abstract: Co-simulation of an electronic circuit design using an embedded processor on a programmable logic device (PLD). The programmable logic resources of a PLD are used to perform hardware-based co-simulation of a first portion of the electronic circuit design. Software-based co-simulation of a second portion of the electronic circuit design is performed using the embedded processor.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: October 14, 2008
    Assignee: Xilinx, Inc.
    Inventors: Jonathan B. Ballagh, L. James Hwang, Roger B. Milne, Nabeel Shirazi, Jeffrey D. Stroomer
  • Patent number: 7433813
    Abstract: Various approaches for embedding a hardware object in an event-driven simulator are disclosed. The various approaches involve generating an HDL proxy component having an HDL definition of each port of the hardware object and respective event handler functions associated with input ports of the HDL proxy component. The event handler functions are responsive to simulation events appearing on the input ports. A configuration bitstream is generated for implementing the hardware object on a programmable logic circuit, and a first object is generated to contain configuration parameter values indicating characteristics of the ports and a location of the configuration bitstream. A second object is generated and is configured to initiate configuration of the programmable logic circuit with the configuration bitstream. The second object further provides input data to and receives output data from the programmable logic circuit.
    Type: Grant
    Filed: May 20, 2004
    Date of Patent: October 7, 2008
    Assignee: Xilinx, Inc.
    Inventors: Jonathan B. Ballagh, L. James Hwang, Roger B. Milne, Nabeel Shirazi