Patents by Inventor L. M. Mahalingam
L. M. Mahalingam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10074588Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate opening in the semiconductor substrate that is partially defined by a recessed surface, and a thermally conductive layer disposed over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate within the active area. A method for fabricating the semiconductor device includes defining an active area, forming a gate electrode over a channel in the active area, forming a source electrode and a drain electrode in the active area on opposite sides of the gate electrode, etching a substrate opening in the semiconductor substrate that is partially defined by the recessed surface, and depositing a thermally conductive layer over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate over the channel.Type: GrantFiled: April 3, 2017Date of Patent: September 11, 2018Assignee: NXP USA, INC.Inventors: Lakshminarayan Viswanathan, Bruce M. Green, Darrell G. Hill, L. M. Mahalingam
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Publication number: 20170207142Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate opening in the semiconductor substrate that is partially defined by a recessed surface, and a thermally conductive layer disposed over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate within the active area. A method for fabricating the semiconductor device includes defining an active area, forming a gate electrode over a channel in the active area, forming a source electrode and a drain electrode in the active area on opposite sides of the gate electrode, etching a substrate opening in the semiconductor substrate that is partially defined by the recessed surface, and depositing a thermally conductive layer over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate over the channel.Type: ApplicationFiled: April 3, 2017Publication date: July 20, 2017Inventors: Lakshminarayan Viswanathan, Bruce M. Green, Darrell G. Hill, L. M. Mahalingam
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Patent number: 9614046Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate opening in the semiconductor substrate that is partially defined by a recessed surface, and a thermally conductive layer disposed over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate within the active area. A method for fabricating the semiconductor device includes defining an active area, forming a gate electrode over a channel in the active area, forming a source electrode and a drain electrode in the active area on opposite sides of the gate electrode, etching a substrate opening in the semiconductor substrate that is partially defined by the recessed surface, and depositing a thermally conductive layer over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate over the channel.Type: GrantFiled: June 3, 2016Date of Patent: April 4, 2017Assignee: NXP USA, INC.Inventors: Lakshminarayan Viswanathan, Bruce M. Green, Darrell G. Hill, L. M. Mahalingam
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Publication number: 20160308010Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate opening in the semiconductor substrate that is partially defined by a recessed surface, and a thermally conductive layer disposed over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate within the active area. A method for fabricating the semiconductor device includes defining an active area, forming a gate electrode over a channel in the active area, forming a source electrode and a drain electrode in the active area on opposite sides of the gate electrode, etching a substrate opening in the semiconductor substrate that is partially defined by the recessed surface, and depositing a thermally conductive layer over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate over the channel.Type: ApplicationFiled: June 3, 2016Publication date: October 20, 2016Inventors: Lakshminarayan Viswanathan, Bruce M. Green, Darrell G. Hill, L. M. Mahalingam
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Patent number: 9425161Abstract: An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.Type: GrantFiled: July 24, 2015Date of Patent: August 23, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Lakshminarayan Viswanathan, L. M. Mahalingam, David F. Abdo, Jaynal A. Molla
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Patent number: 9362198Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate opening in the semiconductor substrate that is partially defined by a recessed surface, and a thermally conductive layer disposed over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate within the active area. A method for fabricating the semiconductor device includes defining an active area, forming a gate electrode over a channel in the active area, forming a source electrode and a drain electrode in the active area on opposite sides of the gate electrode, etching a substrate opening in the semiconductor substrate that is partially defined by the recessed surface, and depositing a thermally conductive layer over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate over the channel.Type: GrantFiled: April 10, 2014Date of Patent: June 7, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Lakshminarayan Viswanathan, Bruce M. Green, Darrell G. Hill, L M Mahalingam
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Patent number: 9337774Abstract: An embodiment of a packaged radio frequency (RF) device includes a device substrate with a voltage reference plane, a first input lead coupled to the device substrate, a first output lead coupled to the device substrate, a first transistor die coupled to a top surface of the device substrate with a solder bond, a second die coupled to the top surface of the device substrate with a conductive epoxy that electrically couples at least one component of the second die to the voltage reference plane, and non-conductive molding compound over the top surface of the device substrate and encompassing the first transistor die, the second die, a portion of the first input lead, and a portion of the first output lead.Type: GrantFiled: September 19, 2014Date of Patent: May 10, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Margaret A. Szymanowski, L. M. Mahalingam, Sarmad K. Musa, Fernando A. Santos, Jerry L. White
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Publication number: 20160087586Abstract: An embodiment of a packaged radio frequency (RF) device includes a device substrate with a voltage reference plane, a first input lead coupled to the device substrate, a first output lead coupled to the device substrate, a first transistor die coupled to a top surface of the device substrate with a solder bond, a second die coupled to the top surface of the device substrate with a conductive epoxy that electrically couples at least one component of the second die to the voltage reference plane, and non-conductive molding compound over the top surface of the device substrate and encompassing the first transistor die, the second die, a portion of the first input lead, and a portion of the first output lead.Type: ApplicationFiled: September 19, 2014Publication date: March 24, 2016Inventors: MARGARET A. SZYMANOWSKI, L.M. MAHALINGAM, SARMAD K. MUSA, FERNANDO A. SANTOS, JERRY L. WHITE
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Publication number: 20150333031Abstract: An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.Type: ApplicationFiled: July 24, 2015Publication date: November 19, 2015Inventors: LAKSHMINARAYAN VISWANATHAN, L.M. MAHALINGAM, DAVID F. ABDO, JAYNAL A. MOLLA
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Publication number: 20150294921Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate opening in the semiconductor substrate that is partially defined by a recessed surface, and a thermally conductive layer disposed over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate within the active area. A method for fabricating the semiconductor device includes defining an active area, forming a gate electrode over a channel in the active area, forming a source electrode and a drain electrode in the active area on opposite sides of the gate electrode, etching a substrate opening in the semiconductor substrate that is partially defined by the recessed surface, and depositing a thermally conductive layer over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate over the channel.Type: ApplicationFiled: April 10, 2014Publication date: October 15, 2015Inventors: LAKSHMINARAYAN VISWANATHAN, Bruce M. Green, Darrell G. Hill, L. M. Mahalingam
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Patent number: 9099567Abstract: An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.Type: GrantFiled: November 25, 2013Date of Patent: August 4, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Lakshminarayan Viswanathan, L. M. Mahalingam, David F. Abdo, Jaynal A. Molla
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Publication number: 20150146399Abstract: An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.Type: ApplicationFiled: November 25, 2013Publication date: May 28, 2015Inventors: LAKSHMINARAYAN VISWANATHAN, L.M. Mahalingam, David F. Abdo, Jaynal A. Molla
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Patent number: 8310042Abstract: A system of mold locks (28, 30) is formed on a heatsink (2) of a packaged semiconductor to prevent/mitigate delamination. The mold locks (4, 12) anchor a plastic mold compound (34) that forms the protective cover for the packaged semiconductor die. The mold locks (4, 12) are miniaturized to allow the positioning of them within the flag portion of the heatsink (2) and leadframe (24) such that a semiconductor die can be anchored above the mold locks (4, 12) formed within the flag portion of the heatsink/lead frame (2, 24). The miniaturized size of the said moldlocks (4, 12 do not detract from the purpose of the die attach solder (36).Type: GrantFiled: June 14, 2006Date of Patent: November 13, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Alexander J. Elliott, L. M. Mahalingam, William M. Strom
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Patent number: 7701074Abstract: An embodiment of a semiconductor device includes a supporting member, a semiconductor die mounted on a portion of the supporting member, a buffer region, and a plastic encapsulation. The buffer region covers a portion of the die, and includes a resin and filler particles packed within the resin. The filler particles have a mix of filler sizes and are tightly packed within the resin. The buffer region has a first dielectric constant and a first loss tangent. The plastic encapsulation encloses at least part of the supporting member and the die. The plastic encapsulation includes a plastic material of a second dielectric constant and a second loss tangent, where the second dielectric constant is larger than the first dielectric constant and the second loss tangent is larger than the first loss tangent.Type: GrantFiled: September 4, 2008Date of Patent: April 20, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Brian W. Condie, L. M. Mahalingam, Mahesh K. Shah
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Publication number: 20040241913Abstract: The disclosures made herein relate to RF power semiconductor devices. In accordance with one embodiment of the disclosures made herein, a RF power plastic semiconductor device comprises a semiconductor (RF) device, a Low Temperature Co-Fired Ceramic (LTCC) impedance matching structure electrically connected to the RF device and a plastic package body formed over the RF device and the impedance matching structure. The LTCC impedance matching structure comprises a metallized layer overlying a major body portion of the impedance matching structure and comprises a passivation layer on the metallized layer. The passivation layer enhances bond strength of a mold compound of the plastic package body to the metallized layer. Portions of the metallized layer are exposed through the passivation layer for enabling electrical interconnects to be formed between the LTCC impedance matching structure and the RF device.Type: ApplicationFiled: May 30, 2003Publication date: December 2, 2004Applicant: Motorola, Inc.Inventors: Robert J. Mclaughlin, Alexander J. Elliott, L. M. Mahalingam, Scott D. Marshall, Pierre-Marie J. Piel
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Publication number: 20040113262Abstract: A system of mold locks (28, 30) is formed on a heatsink (2) of a packaged semiconductor to prevent/mitigate delamination. The mold locks (4, 12) anchor a plastic mold compound (34) that forms the protective cover for the packaged semiconductor die. The mold locks (4, 12) are miniaturized to allow the positioning of them within the flag portion of the heatsink (2) and leadframe (24) such that a semiconductor die can be anchored above the mold locks (4, 12) formed within the flag portion of the heatsink/lead frame (2, 24). The miniaturized size of the said moldlocks (4, 12 do not detract from the purpose of the die attach solder (36).Type: ApplicationFiled: December 13, 2002Publication date: June 17, 2004Applicant: Motorola, Inc.Inventors: Alexander J. Elliott, L.M. Mahalingam, William M. Strom