Abstract: A clock pulse degradation detector monitors the leading and trailing edges of the monitored clock pulse train, and determines the number of leading and trailing edges of the supervised clock pulse train occurring within a single reference pulse. An external oscillator provides an external signal to a reset generator that develops reference pulses having a period less than that of a full cycle of the supervised clock pulse train, but longer than either a single pulse or land of the monitored clock pulse train. Based upon the number of leading and trailing edges detected in the supervised pulse train, a determination is made as to whether the supervised clock train is regular or irregular. Preferably, a pair of two-bit shift registers are utilized to accumulate the number of leading and trailing edges of the supervised clock pulse train. Logic is utilized to determine whether the number of leading and trailing edges stored within these two-bit shift registers indicate a regular or irregular clock pulse train.