Patents by Inventor Léon C. M. van den Oever
Léon C. M. van den Oever has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9998153Abstract: A new front-end module is disclosed. In an embodiment the front-end module is configured to operate carrier aggregation modes using a cascade of switches and an intelligent set of bands. The module can be assembled by sub-modules.Type: GrantFiled: March 14, 2014Date of Patent: June 12, 2018Assignee: SnapTrack, Inc.Inventors: Bart Balm, Carem Destouches, Leon C. M. van den Oever, Ooijman Remco
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Publication number: 20160365878Abstract: A new front-end module is disclosed. In an embodiment the front-end module is configured to operate carrier aggregation modes using a cascade of switches and an intelligent set of bands. The module can be assembled by sub-modules.Type: ApplicationFiled: March 14, 2014Publication date: December 15, 2016Applicants: EPCOS AG, EPCOS AGInventors: Bart Balm, Carem Destouches, Leon C.M. van den Oever, Ooijman Remco
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Patent number: 9306017Abstract: A bipolar transistor includes a substrate of semiconductor material, a high-mobility layer in the substrate, and a donor layer adjacent to the high-mobility layer. An emitter terminal forms an emitter contact on the donor layer, and a collector terminal forms a collector contact on the donor layer. A base terminal is electrically conductively connected with the high-mobility layer. The transistor can be produced in a HEMT technology or BiFET technology in GaAs.Type: GrantFiled: May 17, 2012Date of Patent: April 5, 2016Assignee: EPCOS AGInventors: Léon C. M. van den Oever, Ray J. E. Hueting
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Patent number: 9280169Abstract: A voltage regulator can provide a regulated output voltage. The voltage regulator includes a regulating module that includes a resistor and a field effect transistor that has a threshold voltage. The resistor is coupled to a gate terminal and a source terminal of the field effect transistor. The regulating module provides the output voltage. A reference module is suitable for detecting a variation of the output voltage. The reference module is coupled with the regulating module. A current sink is suitable for subtracting a compensation current from the current flowing from the regulating module to the reference module. The compensation current is dependent on a variation of the threshold voltage.Type: GrantFiled: July 7, 2010Date of Patent: March 8, 2016Assignee: EPCOS AGInventors: Jeroen Bouwman, Leon C. M. van den Oever
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Patent number: 8912847Abstract: A power amplifier circuit (DIPPA), comprising a driver stage (DR) which is applicable to provide a preamplified driver signal (S_DR) dependent on a predetermined transmit signal. The power amplifier circuit (DIPPA) comprises also a frequency selector (DIP) which is electrically coupled to the driver stage (DR) and which is applicable to separate the driver signal (S_DR) into a first and second signal (S—1, S—2). The first signal (S—1) is associated to a first predetermined and the second signal (S—2) is associated to a second predetermined frequency band. The power amplifier circuit (DIPPA) comprises at least a first and second power amplifier stage (PA1, PA2). The first and second power amplifier stage (PA1, PA2) are electrically coupled to the frequency selector (DIP). The first and second power amplifier stage (PA1, PA2) is operable to provide a first and second amplified signal (S_A1, S—2), respectively, dependent on the first and second signal (S—1, S—2), respectively.Type: GrantFiled: December 3, 2009Date of Patent: December 16, 2014Assignee: Epcos AGInventors: Erwin Spits, Leon C. M. van den Oever
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Patent number: 8797100Abstract: Circuit unit (CU) comprising a heterojunction bipolar transistor and a long-gate pseudomorphic high-electron-mobility transistor. Either a source (S) or a drain (D) of the long-gate pseudomorphic high-electron-mobility transistor is electrically coupled with either a collector (C) or an emitter (E) of the heterojunction bipolar transistor.Type: GrantFiled: March 5, 2010Date of Patent: August 5, 2014Assignee: Epcos AGInventors: Bart Balm, Jeroen Bouwman, Léon C. M. van den Oever
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Patent number: 8686752Abstract: A circuit includes a logic stage, an inverter stage, and a driver stage. The logic stage and the inverter stage are provided with current limiters, which include a D-mode feedback transistor and a component that generates a voltage drop. A feedback loop connects the source and the gate of the D-mode feedback transistor via this component. The driver stage includes E-mode transistors connected in a totem pole that drive a D-mode transistor and an E-mode transistor to connect and disconnect the load circuit.Type: GrantFiled: April 26, 2012Date of Patent: April 1, 2014Assignee: EPCOS AGInventors: Léon C. M. van den Oever, Erwin Spits
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Patent number: 8653854Abstract: A circuit includes E-mode transistors with gate-source junction, a D-mode transistor with gate-source junction. A component generates a voltage drop between the source of the D-mode transistor and the drain of an E mode transistor provided as a signal output. A connection is made between this drain of the E-mode transistor and the gate of the D-mode transistor, and a signal input at the gates of the E-mode transistors.Type: GrantFiled: June 15, 2010Date of Patent: February 18, 2014Assignee: EPCOS AGInventors: Erwin Spits, Léon C. M. van den Oever
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Patent number: 8598627Abstract: An n-layer is arranged above a substrate, which can be GaAs, and a p-layer (4) is arranged on the n-layer. The p-layer is separated by a gate electrode into two separate portions forming source and drain. The gate electrode is insulated from the semiconductor material by a gate dielectric. Source/drain contacts are electrically conductively connected with the portions of the p-layer.Type: GrantFiled: November 12, 2009Date of Patent: December 3, 2013Assignee: EPCOS AGInventor: Léon C. M. van den Oever
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Publication number: 20130169250Abstract: A voltage regulator can provide a regulated output voltage. The voltage regulator includes a regulating module that includes a resistor and a field effect transistor that has a threshold voltage. The resistor is coupled to a gate terminal and a source terminal of the field effect transistor. The regulating module provides the output voltage. A reference module is suitable for detecting a variation of the output voltage. The reference module is coupled with the regulating module. A current sink is suitable for subtracting a compensation current from the current flowing from the regulating module to the reference module. The compensation current is dependent on a variation of the threshold voltage.Type: ApplicationFiled: July 7, 2010Publication date: July 4, 2013Applicant: EPCOS AGInventors: Jeroen Bouwman, Leon C.M. van den Oever
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Patent number: 8436663Abstract: A current-limited differential entry stage compares an input signal to a reference voltage generated by a current-limited transistor or diode configuration. Current limiters comprise a D-mode feedback transistor having a gate-source junction. The D-mode transistor is not conducting between the source and the drain if a gate-source voltage is more negative than a negative threshold voltage, and conducting between the source and the drain, otherwise a feedback connection connects the source of the D-mode feedback transistor to its gate via a component that generates a voltage drop.Type: GrantFiled: June 21, 2010Date of Patent: May 7, 2013Assignee: EPCOS AGInventors: Erwin Spits, Léon C. M. van den Oever
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Patent number: 8410572Abstract: A base contact connection, an emitter structure and a collector structure are arranged on an n-layer, which can be provided for additional npn transistors. The collector structure is arranged laterally to the emitter structure and at least one of the emitter and collector comprises a Schottky contact on a surface area of the n-layer.Type: GrantFiled: October 22, 2009Date of Patent: April 2, 2013Assignee: EPCOS AGInventor: Léon C. M. van den Oever
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Publication number: 20130033322Abstract: Circuit unit (CU) comprising a heterojunction bipolar transistor and a long-gate pseudomorphic high-electron-mobility transistor. Either a source (S) or a drain (D) of the long-gate pseudomorphic high-electron-mobility transistor is electrically coupled with either a collector (C) or an emitter (E) of the heterojunction bipolar transistor.Type: ApplicationFiled: March 5, 2010Publication date: February 7, 2013Inventors: Bart Balm, Jeroen Bouwman, Léon C.M. van den Oever
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Patent number: 8305069Abstract: Bandgap reference circuit, comprising a voltage generator (VG) designed to produce a voltage or a current proportional to absolute temperature, a supply circuit (SC), designed to produce a supply for operating the voltage generator (VG), comprising a bias element (BS) and a control element (CS), and a bias circuit (BC), designed to produce a bias for operating the voltage generator (VG), comprising a bias element (BB) and a control element (CB). At least one of the control element (CS) of the supply circuit (SC) and the control element (CB) of the bias circuit (BC) comprises a pseudomorphic high-electron-mobility transistor or a hetero-junction bipolar transistor and/or at least one of the bias element (BS) of the supply circuit (SC) and the bias element (BB) of the bias circuit (BC) comprises a long-gate pseudomorphic high-electron-mobility transistor or a resistor.Type: GrantFiled: March 3, 2011Date of Patent: November 6, 2012Assignee: Epcos AGInventors: Jeroen Bouwman, Léon C. M. van den Oever
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Publication number: 20120268166Abstract: A circuit includes a logic stage, an inverter stage, and a driver stage. The logic stage and the inverter stage are provided with current limiters, which include a D-mode feedback transistor and a component that generates a voltage drop. A feedback loop connects the source and the gate of the D-mode feedback transistor via this component. The driver stage includes E-mode transistors connected in a totem pole that drive a D-mode transistor and an E-mode transistor to connect and disconnect the load circuit.Type: ApplicationFiled: April 26, 2012Publication date: October 25, 2012Applicant: EPCOS AGInventors: Léon C.M. van den Oever, Erwin Spits
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Publication number: 20120235735Abstract: A power amplifier circuit (DIPPA), comprising a driver stage (DR) which is applicable to provide a preamplified driver signal (S_DR) dependent on a predetermined transmit signal. The power amplifier circuit (DIPPA) comprises also a frequency selector (DIP) which is electrically coupled to the driver stage (DR) and which is applicable to separate the driver signal (S_DR) into a first and second signal (S—1, S—2). The first signal (S—1) is associated to a first predetermined and the second signal (S—2) is associated to a second predetermined frequency band. The power amplifier circuit (DIPPA) comprises at least a first and second power amplifier stage (PA1, PA2). The first and second power amplifier stage (PA1, PA2) are electrically coupled to the frequency selector (DIP). The first and second power amplifier stage (PA1, PA2) is operable to provide a first and second amplified signal (S_A1, S—2), respectively, dependent on the first and second signal (S—1, S—2), respectively.Type: ApplicationFiled: December 3, 2009Publication date: September 20, 2012Inventors: Erwin Spits, Leon C.M. van den Oever
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Publication number: 20120112793Abstract: A circuit includes E-mode transistors with gate-source junction, a D-mode transistor with gate-source junction. A component generates a voltage drop between the source of the D-mode transistor and the drain of an E-mode transistor provided as a signal output. A connection is made between this drain of the E-mode transistor and the gate of the D-mode transistor, and a signal input at the gates of the E-mode transistors.Type: ApplicationFiled: June 15, 2010Publication date: May 10, 2012Applicant: Epcos AGInventors: Erwin Spits, Léon C.M. Van den Oever
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Publication number: 20120112801Abstract: A current-limited differential entry stage compares an input signal to a reference voltage generated by a current-limited transistor or diode configuration. Current limiters comprise a D-mode feedback transistor having a gate-source junction. The D-mode transistor is not conducting between the source and the drain if a gate-source voltage is more negative than a negative threshold voltage, and conducting between the source and the drain, otherwise a feedback connection connects the source of the D-mode feedback transistor to its gate via a component that generates a voltage drop.Type: ApplicationFiled: June 21, 2010Publication date: May 10, 2012Applicant: EPCOS AGInventors: Erwin Spits, Léon C.M. van den Oever
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Publication number: 20110248375Abstract: A base contact connection, an emitter structure and a collector structure are arranged on an n-layer, which can be provided for additional npn transistors. The collector structure is arranged laterally to the emitter structure and at least one of the emitter and collector comprises a Schottky contact on a surface area of the n-layer.Type: ApplicationFiled: October 22, 2009Publication date: October 13, 2011Inventor: Léon C. M. Van den Oever
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Publication number: 20110241076Abstract: An n-layer is arranged above a substrate, which can be GaAs, and a p-layer (4) is arranged on the n-layer. The p-layer is separated by a gate electrode into two separate portions forming source and drain. The gate electrode is insulated from the semiconductor material by a gate dielectric. Source/drain contacts are electrically conductively connected with the portions of the p-layer.Type: ApplicationFiled: November 12, 2009Publication date: October 6, 2011Applicant: EPCOS AGInventor: Léon C. M. van den Oever