Abstract: A plug-in JTAG test card includes JTAG boundary scan circuitry which may be used to drive JTAG test data out onto portions of buses connected to peripheral plug-in slots. One or more of the JTAG plug-in test cards can be used to verify the integrity of each of the point-to-point connections on the buses which terminate in the peripheral plug-in slots. In one advantageous embodiment, the plug-in JTAG test cards simulate a dual in-line memory module (DIMM) or single in-line memory module (SIMM) cards which include scan test buffer circuitry but do not actually include memory chips so that an inexpensive plug-in card can be used to provide JTAG testing at the manufacturing level for multiple motherboards. In a particularly preferred embodiment, JTAG boundary scan buffer circuits, such as, for example, SN74ABT8245's, are used as test circuits rather than for their intended use as interface circuits.

Abstract: A docking station for connection with a notebook computer includes a non-volatile memory chip which stores a serial number, an identification number, and configuration information pertaining to the docking station. When a notebook computer engages with the docking station, an electrical connection is provided between a microprocessor within the notebook computer and the non-volatile memory within the docking station so that the microprocessor within the computer 110 can interrogate the memory within the docking station. Based upon the information contained within the non-volatile memory, the software operating system of the notebook computer determines whether or not the notebook computer is compatible with the docking station. Furthermore, if selected configuration information is stored within the non-volatile memory within the docking station, this configuration information can be utilized by the software system of the notebook computer to allocate system resources.

Abstract: Customized circuitry implemented on the transmitting end of an interchip communication bus reduces the number of clock cycles required to transmit control packets over the interchip communication bus. The packet transaction protocol is predicated upon the relationship between consecutive command words sent over the interchip bus so that, if consecutive words at a packet boundary contain the same data, this data can be saved as separate command words by the receiving chip within a single clock cycle. This is accomplished through the generation of a synchronization signal whenever a new packet is started. In a preferred embodiment, bit patterns for the first and/or last word of a packet which are found to be statistically more prevalent are intentionally juxtaposed to increase the probability of consecutive command words having the same information.

Abstract: Specially modified JTAG test circuitry is used to provide test inputs and outputs for vendor supplied megacells with buried I/Os within an integrated circuit chip. A multiplexer or similar circuit is used to alternatively select between a JTAG boundary scan output or a megacell circuit test output in response to JTAG instructions within an instruction register. Additionally, a multiplexer or similar circuit is used to alternatively select between an input pin or normal circuitry for input to a megacell's buried input. Furthermore, an AND or OR gate is used to allow test inputs to a megacell, which are normally tied either high or low, to be controlled by an input pin when in the special JTAG test mode.

Abstract: An interface between first and second data buses includes a first bus state machine which controls data transfers from the first data bus to a data buffer. The interface includes a second bus state machine which controls data transfers from the data buffer to the second data bus. The data buffer includes a plurality of storage locations accessed on a first-in/first-out basis. A respective valid data flag for each storage location is set by the first bus state machine when data are stored in the storage location from the first data bus and is cleared by the second bus state machine when data are transferred from the storage location to the second data bus. The data valid flags are synchronized with first and second bus clocks respectively associated with the first and second bus state machines to assure that the data valid flags change synchronously with respect to each state machine.

Abstract: A circuit utilizes a toggle flip-flop, a D flip-flop and combinatorial logic to generate a clock signal which can be enabled or disabled without creating spikes or shortened pulses in the clock signal. The circuit receives an input clock signal and an input clock enable signal. The circuit generates an output clock signal which is an enabled/disabled version of the input clock signal, controlled by the input clock enable signal. The circuit thus provides the operational advantages of enabling or disabling, with a single control signal, groups of logic circuits triggered by a common clock signal.

Abstract: A memory subsystem includes a posted write buffer for dynamic random access memories (DRAMs). The posted write buffer includes read around logic to enable read accesses to be processed in advance of posted writes. Data are transferred from the posted write buffer to the DRAMs on a general first-in/first out basis; however, in order to take advantage of page mode operation, posted writes having the same row address as a current memory access are given priority over other posted writes such that the posted writes may be written out of order. In addition, comparisons are made between addresses of incoming read accesses and addresses of posted writes in order to expedite the transfer of posted writes having the same row addresses to memory in order to service the incoming read accesses on a timely basis. An improved write access buffer permits posted writes to be transferred to the DRAMs out of order without losing track of the skipped posted writes.

Abstract: An improved method of accessing dynamic random access memory (DRAM) banks during refresh cycles contemplates sequentially accessing DRAM banks which do not share common filtering capacitors. In this manner, voltage drops caused by refresh accesses are not observed in consecutive clock cycles at the same filtering capacitors so that the filtering capacitors will have sufficient recovery time to restore the supply voltage to the original voltage level before another refresh hit occurs at the same capacitor. In this manner, significant voltage drops are alleviated at the voltage supply inputs to the DRAM banks.

Abstract: A method for toggling the output pins of a IC chip to satisfy an ASIC manufacturer's output toggle test requirements parallel loads data from an IC tester into the IC's JTAG boundary scan data shift register, so that the parallel loaded data is an alternating high and low data bits. The test pattern of alternating data bits is then latched to the JTAG data latch register and driven onto the output pins of the IC chip. The bidirectional buffers connected to the output pins are then enabled for output while the IC tester tri-states its alternating data test pattern. The test pattern is then shifted by one bit within the IC's JTAG shift register and parallel loaded into the JTAG latch register on the next clock cycle. In this manner, the complement of a test pattern driven onto the output pins by the external test circuit is driven out from the IC chip.

Abstract: A memory subsystem includes a posted write buffer for dynamic random access memories (DRAMs). The posted write buffer includes read around logic to enable read accesses to be processed in advance of posted writes. Data are transferred from the posted write buffer to the DRAMs on a general first-in/first out basis; however, in order to take advantage of page mode operation, posted writes having the same row address as a current memory access are given priority over other posted writes such that the posted writes may be written out of order. In addition, comparisons are made between addresses of incoming read accesses and addresses of posted writes in order to expedite the transfer of posted writes having the same row addresses to memory in order to service the incoming read accesses on a timely basis. An improved write access buffer permits posted writes to be transferred to the DRAMs out of order without losing track of the skipped posted writes.

Abstract: A specially configured JTAG test circuit allows multiple bus connections within an integrated circuit chip to be selectively placed in a high impedance state in an efficient manner. The output enable shift register locations are placed in close logical proximity to one another along the JTAG data shift register boundary scan path so that data bits need not be shifted into all of the data shift register locations within the integrated circuit chip in order to selectively enable and disable the several bus interfaces within the integrated circuit chip. In this manner, the integrated circuit chip may be isolated from selected ones of the buses connected to the integrated circuit chip, while other bus connections can remain enabled to drive others of the buses connected to the integrated circuit chip. Thus, problems associated with setting the entire integrated circuit chip in a high impedance mode are avoided.

Abstract: An optimum processing frequency is set for processors based upon the individual operational characteristics of each processor. The source voltage supplied to the processor is increased, manually or under software control, to the maximum value specified for the processor. This allows the processor to operate at the maximum possible frequency. The processor clock frequency is varied with respect to the motherboard clock frequency so that the processor clock can be arbitrarily set to its maximum operational frequency. A method of approximation is used to determine the maximum clock frequency at which the processor will function properly. In order to prevent thermally induced semiconductor breakdown, additional heat sinking is performed and/or a thermal management scheme is used. The supply voltage may also be controlled in conjunction with the clock rate to determine the optimum operating frequency and supply voltage to the processor.

Abstract: A circuit utilizes a toggle flip-flop, a D flip-flop and combinatorial logic to generate a clock signal which can be enabled or disabled without creating spikes or shortened pulses in the clock signal. The circuit receives an input clock signal and an input clock enable signal. The circuit generates an output clock signal which is an enabled/disabled version of the input clock signal, controlled by the input clock enable signal. The circuit thus provides the operational advantages of enabling or disabling, with a single control signal, groups of logic circuits triggered by a common clock signal.

Abstract: An input buffer circuit for voltage controlled switch based logic, such as CMOS, which tolerates a floating input voltage without damaging the transistors which form the input buffer circuit. The input buffer circuit protects the input transistors by including an inhibit signal that can be activated to prevent the connection of the system power supply to the system ground when other input signals are floating. The inhibit signal or an independent protection signal further causes the buffer circuit to provide a constant output from the input buffer circuit even when the input voltage floats. Preferred embodiments of the input buffer circuit can be programmed from an internal or external source to cause the output of the buffer circuit to be at an inactive high level or to be at an inactive low level in accordance with whether the input signal being buffered is an inactive high signal or an inactive low signal.