Abstract: A Single Instruction Multiple Data processor apparatus for implementing algorithms using sliding window type data is shown. The implementation shifts the elements of a Destination Vector Register (406, 606) either automatically every time the destination register value is read or in response to a specific instruction (800). The shifting of the Destination Vector Register (406, 606) allows each processing element to operate on new data. As the destination vector (406, 606) elements are shifted, a new element is provided to the vector from a Source Vector Register (404, 604).

Abstract: A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Abstract: A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Abstract: A computer-implemented method is provided for compiling software code that performs nested conditional constructs in vector data processors (10). A vector bit stack (128) to record which processing elements (16) were activated and which processing elements were deactivated during execution of a nested conditional construct. Subsequently, when an end of a first nested conditional construct is encountered, a state of the processing elements at a point in time in which the first nested conditional construct was initiated may be popped off of the vector bit stack and a second conditional construct or any other operation may be executed. Therefore, conditional constructs may be executed while ensuring the proper state of the processing elements. The compiler program effectively utilizes the vector bit stack to store prior states of each of the processing elements of the vector data processor such that the processing elements may be efficiently restored to a correct intermediate value.

Abstract: A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands. The data processing system (55) includes a plurality of instructions which include and utilize an extension bit during execution. In one embodiment, a plurality of instructions, both arithmetic and non-arithmetic, use extension bits for preliminary and non-preliminary instructions in order to accommodate large data widths.

Abstract: A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Abstract: A data processor for storing vector data in multiple locations within the processor using a pointer value and a mask value. In one embodiment, a multi-entry input data register is used to receive input data to be provided to a plurality of processing elements. A pointer value is used to address the multi-entry input data register. A mask value may be used to provide the same data to a plurality of locations within the input data register.

Abstract: A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Abstract: A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Abstract: The present invention, which is implemented in a data processing system, includes a method for performing a fuzzy logic operation, wherein the steps are: (1) performing a rule evaluation process on a plurality of fuzzy input values, wherein one or more of the plurality of fuzzy input values has a lower limit (zero) value, and wherein the rule evaluation process (i) implements a rulebase including a plurality of rules associating a plurality of fuzzy inputs with a plurality of fuzzy outputs, (ii) results in one or more fuzzy output values, and (iii) further includes processing the one or more of the fuzzy input values having the lower limit value with respect to the rulebase, and (2) processing the fuzzy input values having a non-lower limit value with respect to the rulebase, the processing of the fuzzy input values having the non-lower limit value performed separately from the processing of the one or more of the fuzzy input values having the lower limit value.

Abstract: A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Abstract: A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Abstract: A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Abstract: A method for complex data movement in a multi-processor data processing system. In one embodiment, the multi-processor data processing system (10) includes an array (12) of data processors (50-65), a plurality of edge interface circuits (14,16), and a bus interface controller (22). In an alternate embodiment, multiprocessor data processing system (210) includes an array (212) of data processors (250-258), a plurality of edge interface circuits (214-217), and a bus interface controller (222). The data processing systems (10,210) are capable of performing complex data movement patterns between the processors (50-65,250-258) and the corresponding edge interface circuits (14, 16, 214-217), such as a transpose pattern, a ping-pong pattern, and a checkerboard pattern.

Abstract: A "vnmvh" instruction reduces a substantial number of instructions and the temporary use of a register in a software code which executes nested conditional constructs in a vector data processor (10). When the vnmvh instruction is executed, all processing elements in the vector data processor participate in the function regardless of a setting of a status bit (Vt bit) (FIG. 6). During execution of the vnmvh instruction, the least significant bits of vector register specified in an operand are negated and moved into a plurality of history bits (Vh bits) (FIG. 6). The functionality provided by execution of vnmvh instruction allows a user to execute a nested conditional construct efficiently and effectively.

Abstract: A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Abstract: A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Abstract: A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Abstract: A multi-processor data processing system (10) includes an array (12) of one or more data processors (50-65). Data processing system (10) has edge interface circuits (14,16) for transferring control and data to and from the array (12). A data bus (32), an address bus (34), and a control bus (36) each transfers information to and from the array (12), the edge interfaces (14,16), and a bus interface controller (22). In an alternate embodiment, multi-processor data processing system (210) includes an array (212) of one or more data processors (250-258). Data processing system (210) has edge interfaces (214-217) for transferring control and data to and from the array (212). A data bus (232), an address bus (234), and a control bus (236) each transfers information to and from the array (212), the edge interfaces (214-217), and a bus interface controller (222).

Abstract: A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.