Abstract: A controller for a boost power factor correction (PFC) converter. The controller is configured to operate the boost PFC converter in multiple operating modes, including a continuous conduction mode (CCM), a transition mode (TM), and a hybrid mode in which the controller operates the converter in both CCM and TM within a same line cycle. An example controller includes a current control loop and a mode transition circuit. The current control loop is configured to compute an inductor current for each of first and second operation modes, based on a current sample taken, for example, during a boost synchronous rectifier conduction period of the converter. The mode transition circuit includes digital logic circuitry and is configured to generate a pulse indicating that one, two or all three of: zero-voltage switching (ZVS) has been achieved; the synchronous rectifier conduction period is active; and/or one of TM or hybrid mode is active.

Abstract: An apparatus includes a differential input pair, a first resistor, a second resistor, and a comparator. The differential input pair having first and second differential inputs. The first differential input is adapted to be coupled to an output of a controller and the second differential input is adapted to be coupled to a signal ground of the controller. The first resistor is adapted to be coupled to a third resistor via the first differential input to form a first voltage divider. The second resistor is adapted to be coupled to a fourth resistor via the second differential input to form a second voltage divider. The comparator having first and second comparator inputs. The first comparator input is coupled between the first resistor and the first differential input. The second comparator input is coupled between the second resistor and the second differential input.

Abstract: A controller for a boost power factor correction (PFC) converter. The controller is configured to operate the boost PFC converter in multiple operating modes, including a continuous conduction mode (CCM), a transition mode (TM), and a hybrid mode in which the controller operates the converter in both CCM and TM within a same line cycle. An example controller includes a current control loop and a mode transition circuit. The current control loop is configured to compute an inductor current for each of first and second operation modes, based on a current sample taken, for example, during a boost synchronous rectifier conduction period of the converter. The mode transition circuit includes digital logic circuitry and is configured to generate a pulse indicating that one, two or all three of: zero-voltage switching (ZVS) has been achieved; the synchronous rectifier conduction period is active; and/or one of TM or hybrid mode is active.

Abstract: An apparatus includes a differential input pair, a first resistor, a second resistor, and a comparator. The differential input pair having first and second differential inputs. The first differential input is adapted to be coupled to an output of a controller and the second differential input is adapted to be coupled to a signal ground of the controller. The first resistor is adapted to be coupled to a third resistor via the first differential input to form a first voltage divider. The second resistor is adapted to be coupled to a fourth resistor via the second differential input to form a second voltage divider. The comparator having first and second comparator inputs. The first comparator input is coupled between the first resistor and the first differential input. The second comparator input is coupled between the second resistor and the second differential input.

Abstract: The invention relates to the last step of a synthetic process, in which Nomegestrol-acetate of formula (I) is synthesized from 17?-acetoxy-6-methylene-19-norpregn-4-ene-3,20-dione of formula (II) in the presence of Pd/C catalyst and acetic acid in hot ethanolic solution.

Abstract: The invention relates to the last step of a synthetic process, in which Nomegestrol-acetate of formula (I) is synthesized from 17?-acetoxy-6-methylene-19-norpregn-4-ene-3,20-dione of formula (II) in the presence of Pd/C catalyst and acetic acid in hot ethanolic solution.

Abstract: An AC-DC converter includes a main switch that is controlled according to an input AC line voltage. The main switch is allowed to be switched when a level of the input AC line voltage is within a regulation band, and is prevented from being switched when the level of the input AC line voltage is not within the regulation band. The regulation band can be dynamically adjusted based on load condition. The AC-DC converter can be a buck, boost, or buck-boost converter.

Abstract: An AC-DC converter includes a main switch that is controlled according to an input AC line voltage. The main switch is allowed to be switched when a level of the input AC line voltage is within a regulation band, and is prevented from being switched when the level of the input AC line voltage is not within the regulation band. The regulation band can be dynamically adjusted based on load condition. The AC-DC converter can be a buck, boost, or buck-boost converter.

Abstract: The present disclosure is directed to a modulation scheme for driving a piezo element. In one embodiment, a device may comprise, for example, a piezo element, voltage rails and bridge circuitry. The bridge circuitry may be coupled between the piezo element and the voltage rails. The bridge circuitry may include at least signal sources configured to generate drive signals that cause the piezo element to generate mechanical movement while being coupled to at least one of the voltage rails. In the same or a different embodiment the bridge circuitry may further include comparators, the output of the comparators being usable to determine the resonant frequency of the piezo element. The operating frequency of the bridge circuitry may be configured based on the resonant frequency of the piezo element.

Abstract: Driver circuitry and methods are provided for driving a semiconductor device. The driver circuitry includes a buck converter configured to generate a baseline current, and a capacitor coupled between an output of the buck converter and ground, the capacitor configured to store charge during an off-state of the buck converter and to discharge the stored charge as a peak current during an on-state of the buck converter, wherein the baseline current reaches a current limit prior to the capacitor being fully discharged, and an output current at an output of the buck converter is based, at least in part, on the baseline current and the peak current.

Abstract: In an embodiment, a power converter system includes a plurality of variable frequency power converters and a plurality of synchronization circuits. Each variable frequency power converter has a switching frequency. Each synchronization circuit is associated with a respective one of the plurality of variable frequency power converters. A control circuit is coupled to and coordinates the plurality of synchronization circuits. The plurality of synchronization circuits and the control circuit are operable to synchronize the switching frequencies of the variable frequency power converters to each other.

Abstract: A system includes a first switch connected to a voltage input and a switching node. A second switch is connected to the switching node and a reference potential. A first circuit generates first rising edges and first falling edges by comparing a voltage at the switching node to a first voltage reference. The first voltage reference is between the reference potential and the voltage input. A second circuit generates second rising edges and second falling edges by comparing the switching node voltage to a second voltage reference. The second voltage reference is less than the reference potential. The controller calculates delay times based on the first rising edges, the first falling edges, the second rising edges and the second falling edges. The controller generates drive signals for the first switch and the second switch based on a duty cycle and the delay times.

Abstract: In one embodiment, circuitry is provided for startup of a power converter. The circuitry includes a bias capacitor operable to be charged for providing energy to a controller of the power converter. A divider circuit is coupled to a voltage source. Current flows through the divider circuit. A switch, coupled to the divider circuit, is operable to be turned on and off to divert current flow in the divider circuit for charging the bias capacitor. This provides energy to the controller of the power converter at startup without employing an external bias source or high value bleeder resistor.

Abstract: In an embodiment, a power converter system includes a plurality of variable frequency power converters and a plurality of synchronization circuits. Each variable frequency power converter has a switching frequency. Each synchronization circuit is associated with a respective one of the plurality of variable frequency power converters. A control circuit is coupled to and coordinates the plurality of synchronization circuits. The plurality of synchronization circuits and the control circuit are operable to synchronize the switching frequencies of the variable frequency power converters to each other.

Abstract: A system includes a first switch connected to a voltage input and a switching node. A second switch is connected to the switching node and a reference potential. A first circuit generates first rising edges and first falling edges by comparing a voltage at the switching node to a first voltage reference. The first voltage reference is between the reference potential and the voltage input. A second circuit generates second rising edges and second falling edges by comparing the switching node voltage to a second voltage reference. The second voltage reference is less than the reference potential. The controller calculates delay times based on the first rising edges, the first falling edges, the second rising edges and the second falling edges. The controller generates drive signals for the first switch and the second switch based on a duty cycle and the delay times.

Abstract: In an embodiment, a power converter system includes a plurality of variable frequency power converters and a plurality of synchronization circuits. Each variable frequency power converter has a switching frequency. Each synchronization circuit is associated with a respective one of the plurality of variable frequency power converters. A control circuit is coupled to and coordinates the plurality of synchronization circuits. The plurality of synchronization circuits and the control circuit are operable to synchronize the switching frequencies of the variable frequency power converters to each other.

Abstract: Systems and methods control timing of switches in power regulators and power amplifiers. The systems and methods monitor a switch node voltage and obtain rising and falling edges of signals obtained from the monitoring. The systems and methods utilize the rising and falling edges of switch drive signals and predetermined data to obtain delay times for subsequent drive signals.

Abstract: In one embodiment, a method is provided for reducing soft-start delay and ensuring soft recovery from a short circuit or brown out condition in a power converter. The method includes: providing a feedback signal indicative of the output voltage of the power system at a first input terminal of an error amplifier; providing a soft-start reference voltage at a second input terminal of the error amplifier; comparing the feedback signal against the soft-start reference voltage to generate a control signal for regulating an output voltage of the power converter; sourcing current for pre-charging a soft-start capacitor associated with the soft-start reference voltage, thereby reducing soft-start delay; and sinking current for discharging the soft-start capacitor in the event of a short circuit or brown out condition, thereby providing soft recovery after short circuit or brown out events.

Abstract: In one embodiment, a method for soft-start in a power converter includes the following: providing a feedback signal indicative of the output voltage of the power system at a first input terminal of an error amplifier in a negative feedback loop of the power converter; providing a reference voltage at a second input terminal of the error amplifier; comparing the feedback signal against the reference voltage to generate a control signal for regulating an output voltage of the power converter; charging a soft-start capacitor coupled to the second input terminal of the error amplifier with a current for establishing the reference voltage; and adjusting the current in response to the control signal so that the error amplifier is prevented from saturation.

Abstract: In an embodiment, a power converter system includes a plurality of variable frequency power converters and a plurality of synchronization circuits. Each variable frequency power converter has a switching frequency. Each synchronization circuit is associated with a respective one of the plurality of variable frequency power converters. A control circuit is coupled to and coordinates the plurality of synchronization circuits. The plurality of synchronization circuits and the control circuit are operable to synchronize the switching frequencies of the variable frequency power converters to each other.