Abstract: The present invention relates to a mechanism for adaptive run time compilation of traces of program code to achieve efficiency in compilation and overall execution. The mechanism uses a combination of interpretation and compilation in executing byte code. The mechanism selects code segments for compilation based upon frequency of execution and ease of compilation. The inventive mechanism is able to compile small code segments, which can be a subset of a method or subroutine, and comprising only single path execution. The mechanism thereby achieves efficiency in compilation by having less total code as well as having only straight line, or single path execution, code to compile.

Abstract: Method and system for conservatively managing store capacity available to a processor issuing stores are provided and described. In particular, a counter mechanism is utilized, whereas the counter mechanism is incremented or decremented based on the occurrence of particular events.

Abstract: An intelligent network streaming and execution system for conventionally coded applications provides a system that partitions an application program into page segments by observing the manner in which the application program is conventionally installed. A minimal portion of the application program is installed on a client system and the user launches the application in the same ways that applications on other client file systems are started. An application program server streams the page segments to the client as the application program executes on the client and the client stores the page segments in a cache. Page segments are requested by the client from the application server whenever a page fault occurs from the cache for the application program. The client prefetches page segments from the application server or the application server pushes additional page segments to the client based on the pattern of page segment requests for that particular application.

Abstract: Method and system for supporting speculative modification in a data cache are provided and described. A data cache comprises a plurality of cache lines. Each cache line includes a state indicator for indicating anyone of a plurality of states, wherein the plurality of states includes a speculative state to enable keeping track of speculative modification to data in the respective cache line. The speculative state enables a speculative modification to the data in the respective cache line to be made permanent in response to a first operation performed upon reaching a particular instruction boundary during speculative execution of instructions. Further, the speculative state enables the speculative modification to the data in the respective cache line to be undone in response to a second operation performed upon failing to reach the particular instruction boundary during speculative execution of instructions.

Abstract: Method and system for conservatively managing store capacity available to a processor issuing stores are provided and described. In particular, a counter mechanism is utilized, whereas the counter mechanism is incremented or decremented based on the occurrence of particular events.

Abstract: A blocking system intercepts communications between a software program and an operating system in order to handle blocking and unblocking of event signals. The blocking system intercepts system calls to the operating system requesting the blocking and unblocking of event signals and keeps track of which event signals are blocked and unblocked without delivering the system calls to the operating system. The blocking system also intercepts event signals from the operating system and only allows unblocked event signals to pass to the software program. Blocked event signals received by the blocking system are discarded until the program unblocks the blocked event signals. After unblocking an event signal, the blocking system determines whether a corresponding event signal was previously received and blocked. If so, the blocking system transmits a signal indicating that the event corresponding to the event signal occurred.

Abstract: A compiler facilitates efficient unrolling of loops and enables the elimination of extra branches from the loops, including the elimination of conditional branches from unrolled loops with early exits. Unrolling also enhances other optimizations, such as prefetch, scalar replacement, and instruction scheduling. The unroll factor is calculated to determine the amount of loop expansion and the optimum location to place compensation code to complete the original loop count, i.e. before or after the unrolled loop. The compiler is applicable, for example, to modern RISC architectures, where the latency of memory references and branches is higher than that of integer and floating point arithmetic instructions.