Abstract: An integrated priority network is provided for a bus architecture computing system of the type employing a M-Bus connected to a plurality of functional elements. Each functional element has its own integrated priority resolution network (IPRN) coupled to said M-Bus for activating its own unique individual priority request and for receiving all individual priority requests from all other functional elements. Each integrated priority resolution network unit is provided with a rotational priority circuit and a preemptive priority circuit connected in parallel and operable independently to produce a request granted signal. Logic circuits in each rotational priority circuit determine when an IPRN unit will be granted its priority request for access to said M-Bus and will block future requests from being activated to its IPRN unit until the other IPRN unit values in the rotational priority register of the rotational priority circuit have been granted access to said M-Bus.

Abstract: A dual purpose tool for inserting and extracting a PGA multi-in package into associated socket on a PC board.

Abstract: A large scale integrated circuit is designed to handle bus-to-bus data and address transfers, manipulation, and temporary storage. A key feature of the device is that it generates error correcting code parity bits on a byte wide basis so that ECC check bits for a multi-byte word can be generated externally with a minimum of hardware, and includes circuitry responsive to an error syndrome for correcting a single error within a byte. Data manipulation capabilities include standard logical operations, single bit shift operations, binary 2's complement arithmetic addition and subtraction, and decimal addition and subtraction. In addition, an input data byte on any bus can be passed unaltered or inverted to any other bus. The device is capable of receiving operands from one or two of three bidirectional data buses, performing a desired arithmetic or logical operation on the operand or operands, and returning the result to any one of the bidirectional buses including one which may have supplied one of the operands.