Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve data training of a machine learning model using a field-programmable gate array (FPGA). An example system includes one or more computation modules, each of the one or more computation modules associated with a corresponding user, the one or more computation modules training first neural networks using data associated with the corresponding users, and FPGA to obtain a first set of parameters from each of the one or more computation modules, the first set of parameters associated with the first neural networks, configure a second neural network based on the first set of parameters, execute the second neural network to generate a second set of parameters, and transmit the second set of parameters to the first neural networks to update the first neural networks.

Abstract: Embodiments include apparatuses, methods, and systems to provide an automated loading device to a computer assisted or autonomous driving (CA/AD) vehicle. A loading service control device is to initiate a loading service to load one or more items into a storage space of a CA/AD vehicle, using an automated loading device. A CA/AD vehicle is to move to a loading area at an appointed time. A mechanical loading unit of an automated loading device is to place one or more items into a storage space of a CA/AD vehicle. A user device is to receive an input from a user, where the input includes information to generate a request to a loading service control device to load one or more items into a storage space of a CA/AD vehicle using an automated loading device. Other embodiments may also be described and claimed.

Abstract: The present disclosure relates to memory array access control. An apparatus includes partition control circuitry to control at least one partition of a memory array, the at least one partition control circuitry also to receive a controlled clock signal to enable execution of a legitimate memory access command and to generate an active/idle signal having an active state when executing the legitimate memory access command and an idle state when executing the legitimate memory access command is complete; wherein the clock signal is disabled when the active/idle signal is in an idle state.

Abstract: In one embodiment, an apparatus comprises a plurality of memory partitions, each memory partition comprising an array of 3D crosspoint memory, and a storage device controller comprising a memory comprising memory cells to store addresses of replacement memory partitions and addresses of unusable memory partitions and a partition address translation engine coupled to the memory, the partition address translation engine comprising logic to determine whether to redirect a memory access command received from a host computing device to a replacement memory partition based on the contents of the memory.

Abstract: The present disclosure relates to memory array access control. An apparatus includes partition control circuitry to control at least one partition of a memory array, the at least one partition control circuitry also to receive a controlled clock signal to enable execution of a legitimate memory access command and to generate an active/idle signal having an active state when executing the legitimate memory access command and an idle state when executing the legitimate memory access command is complete; wherein the clock signal is disabled when the active/idle signal is in an idle state.