Patents by Inventor Laegu Kang

Laegu Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10483172
    Abstract: A device includes a substrate having an N-active region and a P-active region, a layer of silicon-carbon positioned on an upper surface of the N-active region, a first layer of a first semiconductor material positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on an upper surface of the P-active region, and a layer of a second semiconductor material positioned on the second layer of the first semiconductor material. An N-type transistor is positioned in and above the N-active region and a P-type transistor is positioned in and above the P-active region.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: November 19, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vara G. Reddy Vakada, Laegu Kang, Michael Ganz, Yi Qi, Puneet Khanna, Srikanth Balaji Samavedam, Sri Charan Vemula, Manfred Eller
  • Publication number: 20180047641
    Abstract: A device includes a substrate having an N-active region and a P-active region, a layer of silicon-carbon positioned on an upper surface of the N-active region, a first layer of a first semiconductor material positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on an upper surface of the P-active region, and a layer of a second semiconductor material positioned on the second layer of the first semiconductor material. An N-type transistor is positioned in and above the N-active region and a P-type transistor is positioned in and above the P-active region.
    Type: Application
    Filed: October 24, 2017
    Publication date: February 15, 2018
    Inventors: Vara G. Reddy Vakada, Laegu Kang, Michael Ganz, Yi Qi, Puneet Khanna, Srikanth Balaji Samavedam, Sri Charan Vemula, Manfred Eller
  • Patent number: 9852954
    Abstract: One illustrative method disclosed herein includes performing a first plurality of epitaxial deposition processes to form a first plurality of semiconductor materials selectively above the N-active region while masking the P-active region, performing a second plurality of epitaxial deposition processes to form a second plurality of semiconductor materials selectively above the P-active region while masking the N-active region, forming an N-type transistor in and above the N-active region and forming a P-type transistor in and above the P-active region.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: December 26, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vara G. Reddy Vakada, Laegu Kang, Michael Ganz, Yi Qi, Puneet Khanna, Srikanth Balaji Samavedam, Sri Charan Vemula, Manfred Eller
  • Patent number: 9362357
    Abstract: A method of forming SSRW FETs with controlled step height between a field oxide and epitaxially grown silicon and the resulting devices are provided. Embodiments include providing a SiN layer on a substrate, forming first, second, and third spaced STI regions of field oxide through the SiN layer and into the substrate, removing a top portion of the field oxide for each STI region by a controlled deglaze, removing the SiN layer, forming an n-type region in the substrate between the first and second STI regions and a p-type region in the substrate between the second and third STI regions, and epitaxially growing a Si based layer on the substrate over the n-type and p-type regions.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: June 7, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Laegu Kang, Vara Govindeswara Reddy Vakada, Michael Ganz, Yi Qi, Puneet Khanna, Sri Charan Vemula, Srikanth Samavedam
  • Publication number: 20160035630
    Abstract: One illustrative method disclosed herein includes performing a first plurality of epitaxial deposition processes to form a first plurality of semiconductor materials selectively above the N-active region while masking the P-active region, performing a second plurality of epitaxial deposition processes to form a second plurality of semiconductor materials selectively above the P-active region while masking the N-active region, forming an N-type transistor in and above the N-active region and forming a P-type transistor in and above the P-active region.
    Type: Application
    Filed: October 14, 2015
    Publication date: February 4, 2016
    Inventors: Vara G. Reddy Vakada, Laegu Kang, Michael Ganz, Yi Qi, Puneet Khanna, Srikanth Balaji Samavedam, Sri Charan Vemula, Manfred Eller
  • Patent number: 9209181
    Abstract: A method includes forming a layer of silicon-carbon on an N-active region, performing a common deposition process to form a layer of a first semiconductor material on the layer of silicon-carbon and on the P-active region, masking the N-active region, forming a layer of a second semiconductor material on the first semiconductor material in the P-active region and forming N-type and P-type transistors. A device includes a layer of silicon-carbon positioned on an N-active region, a first layer of a first semiconductor positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on a P-active region, a layer of a second semiconductor material positioned on the second layer of the first semiconductor material, and N-type and P-type transistors.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: December 8, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vara G. Reddy Vakada, Laegu Kang, Michael Ganz, Yi Qi, Puneet Khanna, Srikanth Balaji Samavedam, Sri Charan Vemula, Manfred Eller
  • Publication number: 20150249129
    Abstract: A method of forming SSRW FETs with controlled step height between a field oxide and epitaxially grown silicon and the resulting devices are provided. Embodiments include providing a SiN layer on a substrate, forming first, second, and third spaced STI regions of field oxide through the SiN layer and into the substrate, removing a top portion of the field oxide for each STI region by a controlled deglaze, removing the SiN layer, forming an n-type region in the substrate between the first and second STI regions and a p-type region in the substrate between the second and third STI regions, and epitaxially growing a Si based layer on the substrate over the n-type and p-type regions.
    Type: Application
    Filed: May 19, 2015
    Publication date: September 3, 2015
    Inventors: Laegu KANG, Vara Govindeswara Reddy VAKADA, Michael GANZ, Yi QI, Puneet KHANNA, Sri Charan VEMULA, Srikanth SAMAVEDAM
  • Patent number: 9099525
    Abstract: A method of forming SSRW FETs with controlled step height between a field oxide and epitaxially grown silicon and the resulting devices are provided. Embodiments include providing a SiN layer on a substrate, forming first, second, and third spaced STI regions of field oxide through the SiN layer and into the substrate, removing a top portion of the field oxide for each STI region by a controlled deglaze, removing the SiN layer, forming an n-type region in the substrate between the first and second STI regions and a p-type region in the substrate between the second and third STI regions, and epitaxially growing a Si based layer on the substrate over the n-type and p-type regions.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: August 4, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Laegu Kang, Vara Govindeswara Reddy Vakada, Michael P. Ganz, Yi Qi, Puneet Khanna, Sri Charan Vemula, Srikanth Samavedam
  • Patent number: 9099380
    Abstract: A methodology enabling the formation of steep channel profiles for devices, such as SSRW FETs, having a resultant channel profiles that enables suppression of threshold voltage variation and the resulting device are disclosed. Embodiments include providing STI regions in a silicon wafer; performing a deep well implantation of a dopant into the silicon wafer between STI regions; forming a recess in the doped silicon wafer between the STI regions; performing a shallow well implantation of the dopant into the silicon wafer in the recess; and forming Si:C on the doped silicon wafer in the recess.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: August 4, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vara Govindeswara Reddy Vakada, Laegu Kang, Michael P. Ganz, Yi Qi, Puneet Khanna, Sri Charan Vemula, Srikanth Samavedam
  • Publication number: 20150053981
    Abstract: A methodology enabling the formation of steep channel profiles for devices, such as SSRW FETs, having a resultant channel profiles that enables suppression of threshold voltage variation and the resulting device are disclosed. Embodiments include providing STI regions in a silicon wafer; performing a deep well implantation of a dopant into the silicon wafer between STI regions; forming a recess in the doped silicon wafer between the STI regions; performing a shallow well implantation of the dopant into the silicon wafer in the recess; and forming Si:C on the doped silicon wafer in the recess.
    Type: Application
    Filed: October 10, 2014
    Publication date: February 26, 2015
    Inventors: Vara Govindeswara Reddy VAKADA, Laegu KANG, Michael P. GANZ, Yi QI, Puneet KHANNA, Sri Charan VEMULA, Srikanth SAMAVEDAM
  • Patent number: 8916442
    Abstract: A methodology enabling the formation of steep channel profiles for devices, such as SSRW FETs, having a resultant channel profiles that enables suppression of threshold voltage variation and the resulting device are disclosed. Embodiments include providing STI regions in a silicon wafer; performing a deep well implantation of a dopant into the silicon wafer between STI regions; forming a recess in the doped silicon wafer between the STI regions; performing a shallow well implantation of the dopant into the silicon wafer in the recess; and forming Si:C on the doped silicon wafer in the recess.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: December 23, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vara Govindeswara Reddy Vakada, Laegu Kang, Michael P. Ganz, Yi Qi, Puneet Khanna, Sri Charan Vemula, Srikanth Samavedam
  • Publication number: 20140367787
    Abstract: A method includes forming a layer of silicon-carbon on an N-active region, performing a common deposition process to form a layer of a first semiconductor material on the layer of silicon-carbon and on the P-active region, masking the N-active region, forming a layer of a second semiconductor material on the first semiconductor material in the P-active region and forming N-type and P-type transistors. A device includes a layer of silicon-carbon positioned on an N-active region, a first layer of a first semiconductor positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on a P-active region, a layer of a second semiconductor material positioned on the second layer of the first semiconductor material, and N-type and P-type transistors.
    Type: Application
    Filed: June 14, 2013
    Publication date: December 18, 2014
    Inventors: Vara G. Reddy Vakada, Laegu Kang, Michael Ganz, Yi Qi, Puneet Khanna, Srikanth Balaji Samavedam, Sri Charan Vemula, Manfred Eller
  • Patent number: 8809178
    Abstract: One illustrative method disclosed herein includes forming a plurality of spaced-apart trenches in a semiconducting substrate to thereby define a fin structure for the device, forming a local isolation region within each of the trenches, forming a sacrificial gate structure on the fin structure, wherein the sacrificial gate structure comprises at least a sacrificial gate electrode, and forming a layer of insulating material above the fin structure and within the trench above the local isolation region. In this example, the method further includes performing at least one etching process to remove the sacrificial gate structure to thereby define a gate cavity, after removing the sacrificial gate structure, performing at least one etching process to form a recess in the local isolation region, and forming a replacement gate structure that is positioned in the recess in the local isolation region and in the gate cavity.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: August 19, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yanxiang Liu, Michael Hargrove, Xiaodong Yang, Hans van Meer, Laegu Kang, Christian Gruensfelder, Srikanth Samavedam
  • Patent number: 8790972
    Abstract: Methods of forming integrated circuit devices include forming a PMOS transistor having a SiGe channel region therein and then exposing at least a portion of the PMOS transistor to a hydrogen plasma. A tensile stress layer may be formed on the PMOS transistor. The exposing step may include exposing source and drain regions of the PMOS transistor to the hydrogen plasma.
    Type: Grant
    Filed: August 19, 2010
    Date of Patent: July 29, 2014
    Assignees: Samsung Electronics Co., Ltd., International Business Machines Corporation, GLOBALFOUNDRIES Singapore Pte. Ltd., Freescale Semiconductor, Inc.
    Inventors: Yong-Kuk Jeong, Laegu Kang, Kim Nam Sung, Dae-won Yang
  • Publication number: 20140197411
    Abstract: A methodology enabling the formation of steep channel profiles for devices, such as SSRW FETs, having a resultant channel profiles that enables suppression of threshold voltage variation and the resulting device are disclosed. Embodiments include providing STI regions in a silicon wafer; performing a deep well implantation of a dopant into the silicon wafer between STI regions; forming a recess in the doped silicon wafer between the STI regions; performing a shallow well implantation of the dopant into the silicon wafer in the recess; and forming Si:C on the doped silicon wafer in the recess.
    Type: Application
    Filed: January 17, 2013
    Publication date: July 17, 2014
    Applicant: GLOBAL FOUNDERIES INC.
    Inventors: Vara Govindeswara Reddy VAKADA, Laegu Kang, Michael P. Ganz, Yi Qi, Puneet Khanna, Sri Charan Vemula, Srikanth Samavedam
  • Publication number: 20140183551
    Abstract: A method of forming SSRW FETs with controlled step height between a field oxide and epitaxially grown silicon and the resulting devices are provided. Embodiments include providing a SiN layer on a substrate, forming first, second, and third spaced STI regions of field oxide through the SiN layer and into the substrate, removing a top portion of the field oxide for each STI region by a controlled deglaze, removing the SiN layer, forming an n-type region in the substrate between the first and second STI regions and a p-type region in the substrate between the second and third STI regions, and epitaxially growing a Si based layer on the substrate over the n-type and p-type regions.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Laegu Kang, Vara Govindeswara Reddy Vakada, Michael P. Ganz, Yi Qi, Puneet Khanna, Sri Charan Vemula, Srikanth Samavedam
  • Publication number: 20140070358
    Abstract: A methodology is disclosed enabling the formation of silicon trench profiles for devices, such as SSRW FETs, having a resultant profile that enables desirable epitaxial growth of semiconductor materials. Embodiments include forming a trench in a silicon wafer between STI regions, thermally treating the silicon surfaces of the trench, and forming Si:C in the trench. The process eliminates a need for an isotropic silicon etch to achieve a desirable flat surface. Further, the flat bottom surface provides a desirable surface for epitaxial growth of semiconductor materials, such as Si:C.
    Type: Application
    Filed: September 12, 2012
    Publication date: March 13, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Yi Qi, Puneet Khanna, Srikanth Samavedam, Vara G. Vakada, Michael P. Ganz, Sri Charan Vemula, Laegu Kang, Bharat V. Krishnan
  • Publication number: 20130224945
    Abstract: One illustrative method disclosed herein includes forming a plurality of spaced-apart trenches in a semiconducting substrate to thereby define a fin structure for the device, forming a local isolation region within each of the trenches, forming a sacrificial gate structure on the fin structure, wherein the sacrificial gate structure comprises at least a sacrificial gate electrode, and forming a layer of insulating material above the fin structure and within the trench above the local isolation region. In this example, the method further includes performing at least one etching process to remove the sacrificial gate structure to thereby define a gate cavity, after removing the sacrificial gate structure, performing at least one etching process to form a recess in the local isolation region, and forming a replacement gate structure that is positioned in the recess in the local isolation region and in the gate cavity.
    Type: Application
    Filed: February 29, 2012
    Publication date: August 29, 2013
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Yanxiang Liu, Michael Hargrove, Xiaodong Yang, Hans Van Meer, Laegu Kang, Christian Gruensfelder, Srikanth Samavedam
  • Patent number: 8445969
    Abstract: An integrated circuit structure comprises at least one pair of complementary transistors on a substrate. The pair of complementary transistors includes a first transistor and a second transistor. In addition, only one stress-producing layer is on the first transistor and the second transistor and applies tensile strain force on the first transistor and the second transistor. The first transistor has a first channel region, a gate insulator on the first channel region, and a deuterium region between the first channel region and the gate insulator. The second transistor has a germanium doped channel region, as well as the same gate insulator on the germanium doped channel region, and the same deuterium region between the germanium doped channel region and the gate insulator.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: May 21, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xiangdong Chen, Laegu Kang, Weipeng Li, Dae-Gyu Park, Melanie J. Sherony
  • Publication number: 20120273894
    Abstract: An integrated circuit structure comprises at least one pair of complementary transistors on a substrate. The pair of complementary transistors includes a first transistor and a second transistor. In addition, only one stress-producing layer is on the first transistor and the second transistor and applies tensile strain force on the first transistor and the second transistor. The first transistor has a first channel region, a gate insulator on the first channel region, and a deuterium region between the first channel region and the gate insulator. The second transistor has a germanium doped channel region, as well as the same gate insulator on the germanium doped channel region, and the same deuterium region between the germanium doped channel region and the gate insulator.
    Type: Application
    Filed: April 27, 2011
    Publication date: November 1, 2012
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, FREESCALE SEMICONDUCTOR, INC.
    Inventors: Xiangdong Chen, Laegu Kang, Weipeng Li, Dae-Gyu Park, Melanie J. Sherony