Patents by Inventor Lai Beng TEOH

Lai Beng TEOH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High performance low profile QFN/LGA
    Patent number: 9165795
    Abstract: A method for manufacturing a semiconductor device is disclosed. In one embodiment a semiconductor die is formed overlying a substrate. The semiconductor die is flip chip mounted to the substrate, wherein the substrate comprises a plurality of conductive traces. The semiconductor die and substrate are encapsulated with an encapsulating material. A top side of the encapsulating material is subjected to one of polishing, etching, and grinding to expose a top side of the semiconductor die. Finally, the bottom side of the substrate is subjected to one of polishing, etching, and grinding to remove the substrate and to reduce a thickness of the plurality of conductive traces.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: October 20, 2015
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Gin Ghee Tan, Lai Beng Teoh, Lay Hong Lee
  • Device having multiple wire bonds for a bond area and methods thereof
    Patent number: 8791007
    Abstract: Wire bonds are formed at an integrated circuit device so that multiple wires are bonded to a single bond pad. In a particular embodiment, the multiple wires are bonded by first applying a stud bump to the pad and successively bonding each of the wires to the stud bump. Another stud bump can be placed over the bonded wires to provide additional connection security.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: July 29, 2014
    Assignee: Spansion LLC
    Inventors: Gin Ghee Tan, Lai Beng Teoh, Royce Yeoh Kao Tziat, Sally Yin Lye Foong
  • DEVICE HAVING MULTIPLE WIRE BONDS FOR A BOND AREA AND METHODS THEREOF
    Publication number: 20130134578
    Abstract: Wire bonds are formed at an integrated circuit device so that multiple wires are bonded to a single bond pad. In a particular embodiment, the multiple wires are bonded by first applying a stud bump to the pad and successively bonding each of the wires to the stud bump. Another stud bump can be placed over the bonded wires to provide additional connection security.
    Type: Application
    Filed: November 29, 2011
    Publication date: May 30, 2013
    Applicant: SPANSION LLC
    Inventors: Gin Ghee Tan, Lai Beng Teoh, Royce Yeoh Kao Tziat, Sally Foong Yin Lye
  • HIGH PERFORMANCE LOW PROFILE QFN/LGA
    Publication number: 20120146213
    Abstract: A method for manufacturing a semiconductor device is disclosed. In one embodiment a semiconductor die is formed overlying a substrate. The semiconductor die is flip chip mounted to the substrate, wherein the substrate comprises a plurality of conductive traces. The semiconductor die and substrate are encapsulated with an encapsulating material. A top side of the encapsulating material is subjected to one of polishing, etching, and grinding to expose a top side of the semiconductor die. Finally, the bottom side of the substrate is subjected to one of polishing, etching, and grinding to remove the substrate and to reduce a thickness of the plurality of conductive traces.
    Type: Application
    Filed: December 9, 2010
    Publication date: June 14, 2012
    Inventors: Gin Ghee TAN, Lai Beng TEOH, Lay Hong LEE