Patents by Inventor Lai Chien Wen
Lai Chien Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200004137Abstract: A photo mask for manufacturing a semiconductor device includes a first pattern extending in a first direction, a second pattern extending in the first direction and aligned with the first pattern, and a sub-resolution pattern extending in the first direction, disposed between an end of the first pattern and an end of the second pattern. A width of the first pattern and a width of the second pattern are equal to each other, and the first pattern and the second pattern are for separate circuit elements in the semiconductor device.Type: ApplicationFiled: February 27, 2019Publication date: January 2, 2020Inventors: Ru-Gun LIU, Chin-Hsiang LIN, Cheng-I HUANG, Chih-Ming LAI, Lai Chien WEN, Ken-Hsien HSIEH, Shih-Ming CHANG, Yuan-Te HOU
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Publication number: 20190148145Abstract: A method of fabricating a semiconductor device includes forming a hard mask layer over a substrate. A multi-layer resist is formed over the hard mask layer. The multi-layer resist is etched to form a plurality of openings in the multi-layer resist to expose a portion of the hard mask layer. Ion are directionally provided at an angle to the multi-layer resist to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer. In one embodiment, the multi-layer resist is directionally etched by directing etch ions at an angle to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer. In another embodiment, the multi-layer resist is directionally implanted by directing implant ions at an angle to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer.Type: ApplicationFiled: November 14, 2017Publication date: May 16, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Chun Huang, Chin-Hsiang Lin, Lai Chien Wen, Ru-Gun Liu, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Yu-Tien Shen, Ya-Wen Yeh
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Patent number: 9496217Abstract: The present disclosure provides a semiconductor device that includes, a substrate; a first conductive line located over the substrate and extending along a first axis, the first conductive line having a first length and a first width, the first length being measured along the first axis; a second conductive line located over the first conductive line and extending along a second axis different from the first axis, the second conductive line having a second length and a second width, the second length being measured along the second axis; and a via coupling the first and second conductive lines, the via having an upper surface that contacts the second conductive line and a lower surface that contacts the first conductive line. The via has an approximately straight edge at the upper surface, the straight edge extending along the second axis and being substantially aligned with the second conductive line.Type: GrantFiled: June 4, 2009Date of Patent: November 15, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Yi Tsai, Chih-Hao Chen, Ming-Chung Liang, Chii-Ping Chen, Lai Chien Wen, Yuh-Jier Mii
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Patent number: 8589830Abstract: Provided is an integrated circuit (IC) design method. The method includes receiving an IC design layout having a feature with an outer boundary, performing a dissection on the feature to divide the outer boundary into a plurality of segments, and performing, using the segments, an optical proximity correction (OPC) on the feature to generate a modified outer boundary. The method also includes simulating a photolithography exposure of the feature with the modified outer boundary to create a contour and performing an OPC evaluation to determine if the contour is within a threshold. Additionally, the method includes repeating the performing a dissection, the performing an optical proximity correction, and the simulating if the contour does not meet the threshold, wherein each repeated dissection and each repeated optical proximity correction is performed on the modified outer boundary generated by the previously performed optical proximity correction.Type: GrantFiled: March 7, 2012Date of Patent: November 19, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Cheng Chang, Chin-Min Huang, Wei-Kuan Yu, Cherng-Shyan Tsay, Lai Chien Wen, Hua-Tai Lin
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Publication number: 20130239071Abstract: Provided is an integrated circuit (IC) design method. The method includes receiving an IC design layout having a feature with an outer boundary, performing a dissection on the feature to divide the outer boundary into a plurality of segments, and performing, using the segments, an optical proximity correction (OPC) on the feature to generate a modified outer boundary. The method also includes simulating a photolithography exposure of the feature with the modified outer boundary to create a contour and performing an OPC evaluation to determine if the contour is within a threshold. Additionally, the method includes repeating the performing a dissection, the performing an optical proximity correction, and the simulating if the contour does not meet the threshold, wherein each repeated dissection and each repeated optical proximity correction is performed on the modified outer boundary generated by the previously performed optical proximity correction.Type: ApplicationFiled: March 7, 2012Publication date: September 12, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Cheng Chang, Chin-Min Huang, Wei-Kuan Yu, Cherng-Shyan Tsay, Lai Chien Wen, Hua-Tai Lin
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Patent number: 7960821Abstract: An integrated circuit device and method of making the integrated circuit device are disclosed. An exemplary apparatus includes: a semiconductor layer; and a dielectric layer on the semiconductor layer, the dielectric layer having conductive vias and dummy vias formed therein, wherein the conductive vias and dummy vias extend varying distances into the dielectric layer, the conductive vias extending through the dielectric layer to the semiconductor layer, and the dummy vias extending through the dielectric layer to a distance above the semiconductor layer.Type: GrantFiled: March 3, 2010Date of Patent: June 14, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei Shun Chen, Chin-Hsiang Lin, Vencent Chang, Lawrence Lin, Lai Chien Wen, Jhun Hua Chen
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Patent number: 7939222Abstract: A photolithography system for printing a pattern of at least one contact or via on a wafer is provided. The system comprises a reticle having a layout, the layout comprises at least one polygon-shaped hole, wherein the at least one polygon-shaped hole comprises at least eight sides.Type: GrantFiled: March 16, 2007Date of Patent: May 10, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jhun-Hua Chen, Hua-Tai Lin, Lai Chien Wen, Fu-Jye Liang
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Publication number: 20100308469Abstract: The present disclosure provides a semiconductor device that includes, a substrate; a first conductive line located over the substrate and extending along a first axis, the first conductive line having a first length and a first width, the first length being measured along the first axis; a second conductive line located over the first conductive line and extending along a second axis different from the first axis, the second conductive line having a second length and a second width, the second length being measured along the second axis; and a via coupling the first and second conductive lines, the via having an upper surface that contacts the second conductive line and a lower surface that contacts the first conductive line. The via has an approximately straight edge at the upper surface, the straight edge extending along the second axis and being substantially aligned with the second conductive line.Type: ApplicationFiled: June 4, 2009Publication date: December 9, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Yi Tsai, Chih-Hao Chen, Ming-Chung Liang, Chii-Ping Chen, Lai Chien Wen, Yuh-Jier Mii
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Patent number: 7767570Abstract: A method of making an integrated circuit includes providing a low-k dielectric layer on a substrate, the low-k dielectric layer including or adjacent to a plurality of conductive features; patterning the low-k dielectric layer to form trenches; patterning the low-k dielectric layer to form conductive vias and dummy vias, wherein each of the conductive vias is aligned with at least one of the plurality of the conductive features and at least one of the trenches, and each of the dummy vias is a distance above the plurality of conductive features; filling the trenches, conductive vias, and dummy vias using one or more conductive materials; and planarizing the conductive material(s).Type: GrantFiled: July 12, 2006Date of Patent: August 3, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei Shun Chen, Chin-Hsiang Lin, Vencent Chang, Lawrence Lin, Lai Chien Wen, Jhun Hua Chen
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Publication number: 20100155963Abstract: An integrated circuit device and method of making the integrated circuit device are disclosed. An exemplary apparatus includes: a semiconductor layer; and a dielectric layer on the semiconductor layer, the dielectric layer having conductive vias and dummy vias formed therein, wherein the conductive vias and dummy vias extend varying distances into the dielectric layer, the conductive vias extending through the dielectric layer to the semiconductor layer, and the dummy vias extending through the dielectric layer to a distance above the semiconductor layer.Type: ApplicationFiled: March 3, 2010Publication date: June 24, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuei Shun Chen, Chin-Hsiang Lin, Vencent Chang, Lawrence Lin, Lai Chien Wen, Jhun Hua Chen
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Publication number: 20080226996Abstract: A photolithography system for printing a pattern of at least one contact or via on a wafer is provided. The system comprises a reticle having a layout, the layout comprises at least one polygon-shaped hole, wherein the at least one polygon-shaped hole comprises at least eight sides.Type: ApplicationFiled: March 16, 2007Publication date: September 18, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jhun-Hua Chen, Hua-Tai Lin, Lai Chien Wen, Fu-Jye Liang
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Publication number: 20070224795Abstract: A method of making an integrated circuit includes providing a low-k dielectric layer on a substrate, the low-k dielectric layer including or adjacent to a plurality of conductive features; patterning the low-k dielectric layer to form trenches; patterning the low-k dielectric layer to form conductive vias and dummy vias, wherein each of the conductive vias is aligned with at least one of the plurality of the conductive features and at least one of the trenches, and each of the dummy vias is a distance above the plurality of conductive features; filling the trenches, conductive vias, and dummy vias using one or more conductive materials; and planarizing the conductive material(s).Type: ApplicationFiled: July 12, 2006Publication date: September 27, 2007Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuei Shun CHEN, Chin-Hsiang LIN, Vencent CHANG, Lawrence LIN, Lai Chien WEN, Jhun Hua CHEN