Abstract: An amplifier system includes a main amplifier, a cross-over current detector and a controller. The main amplifier includes at least a first driving transistor and a second driving transistor serving as a differential pair, wherein the first driving transistor and the second driving transistor are arranged to receive a first input signal and a second input signal, respectively. The cross-over current detector is coupled to the main amplifier, and is arranged for detecting a cross-over current of the main amplifier, wherein the cross-over current of the main amplifier is an overlapped current from the differential pair. The controller is coupled to the main amplifier and the cross-over current detector, and is arranged for generating a control signal to control a gain of the main amplifier according to an output of the main amplifier and the cross-over current of the main amplifier.

Abstract: The present invention provides a control circuit to stabilize an output power of a power amplifier. The control circuit comprises a voltage clamping loop, a current clamping loop and a loop for reducing power variation under VSWR, where the voltage clamping loop is used to clamp an output voltage of the power amplifier within a defined voltage range, the current clamping loop is used to clamp a current of the power amplifier within a defined current range, and the loop for reducing power variation under VSWR is implemented by an impedance detector to compensate the output power under VSWR variation.

Abstract: An amplifier system includes a main amplifier, a cross-over current detector and a controller. The main amplifier includes at least a first driving transistor and a second driving transistor serving as a differential pair, wherein the first driving transistor and the second driving transistor are arranged to receive a first input signal and a second input signal, respectively. The cross-over current detector is coupled to the main amplifier, and is arranged for detecting a cross-over current of the main amplifier, wherein the cross-over current of the main amplifier is an overlapped current from the differential pair. The controller is coupled to the main amplifier and the cross-over current detector, and is arranged for generating a control signal to control a gain of the main amplifier according to an output of the main amplifier and the cross-over current of the main amplifier.

Abstract: An amplifier system includes a main amplifier, a cross-over current detector and a controller. The main amplifier includes at least a first driving transistor and a second driving transistor serving as a differential pair, wherein the first driving transistor and the second driving transistor are arranged to receive a first input signal and a second input signal, respectively. The cross-over current detector is coupled to the main amplifier, and is arranged for detecting a cross-over current of the main amplifier, wherein the cross-over current of the main amplifier is an overlapped current from the differential pair. The controller is coupled to the main amplifier and the cross-over current detector, and is arranged for generating a control signal to control a gain of the main amplifier according to an output of the main amplifier and the cross-over current of the main amplifier.

Abstract: The present invention provides a control circuit to stabilize an output power of a power amplifier. The control circuit comprises a voltage clamping loop, a current clamping loop and a loop for reducing power variation under VSWR, where the voltage clamping loop is used to clamp an output voltage of the power amplifier within a defined voltage range, the current clamping loop is used to clamp a current of the power amplifier within a defined current range, and the loop for reducing power variation under VSWR is implemented by an impedance detector to compensate the output power under VSWR variation.

Abstract: An amplifier system includes a main amplifier, a cross-over current detector and a controller. The main amplifier includes at least a first driving transistor and a second driving transistor serving as a differential pair, wherein the first driving transistor and the second driving transistor are arranged to receive a first input signal and a second input signal, respectively. The cross-over current detector is coupled to the main amplifier, and is arranged for detecting a cross-over current of the main amplifier, wherein the cross-over current of the main amplifier is an overlapped current from the differential pair. The controller is coupled to the main amplifier and the cross-over current detector, and is arranged for generating a control signal to control a gain of the main amplifier according to an output of the main amplifier and the cross-over current of the main amplifier.

Abstract: A variable gain amplifier circuit comprises a main amplifier, a current sensing circuit, a variable loading and a control amplifier. The main amplifier is configured for amplifying an input signal to generate an output signal. The current sensing circuit is coupled to the main amplifier, and is configured for generating a sensed current related to a current flowing through the main amplifier. The variable loading is coupled to the current mirror via a node, wherein the sensed current flows through the node and the variable loading. The control amplifier is coupled to the node and the main amplifier, and is configured for receiving a control voltage and a voltage of the node to generate an adjustment signal to control a gain of the main amplifier, wherein a resistance of the variable loading has a nonlinear relationship with the control voltage.

Abstract: A variable gain amplifier circuit comprises a main amplifier, a current sensing circuit, a variable loading and a control amplifier. The main amplifier is configured for amplifying an input signal to generate an output signal. The current sensing circuit is coupled to the main amplifier, and is configured for generating a sensed current related to a current flowing through the main amplifier. The variable loading is coupled to the current mirror via a node, wherein the sensed current flows through the node and the variable loading. The control amplifier is coupled to the node and the main amplifier, and is configured for receiving a control voltage and a voltage of the node to generate an adjustment signal to control a gain of the main amplifier, wherein a resistance of the variable loading has a nonlinear relationship with the control voltage.

Abstract: The switch circuit comprises a first switch, a second switch, a third switch, a forth switch, a fifth switch, a sixth switch and a seventh switch. The first switch couples the voltage input terminal to one terminal of a flying capacitor. The second switch couples one terminal of the flying capacitor to one terminal of the output capacitor. The third switch couples one terminal of the flying capacitor to a common terminal. The fourth switch couples the other terminal of the flying capacitor to one terminal of the output capacitor. The fifth switch couples one terminal of the output capacitor to a positive voltage output terminal. The sixth switch couples the other terminal of the flying capacitor to the common terminal. The seventh switch couples the other terminal of the flying capacitor to a negative voltage output terminal.

Abstract: The switch circuit comprises a first switch, a second switch, a third switch, a forth switch, a fifth switch, a sixth switch and a seventh switch. The first switch couples the voltage input terminal to one terminal of a flying capacitor. The second switch couples one terminal of the flying capacitor to one terminal of the output capacitor. The third switch couples one terminal of the flying capacitor to a common terminal. The fourth switch couples the other terminal of the flying capacitor to one terminal of the output capacitor. The fifth switch couples one terminal of the output capacitor to a positive voltage output terminal. The sixth switch couples the other terminal of the flying capacitor to the common terminal. The seventh switch couples the other terminal of the flying capacitor to a negative voltage output terminal.

Abstract: A switched capacitor digital-to-analog converter (SC-DAC) is provided. The SC-DAC of the present invention can eliminate an influence of a reference voltage source caused by a signal dependent loading at each clock cycle, so as to completely solve a harmonic distortion of an analog output signal converted by a conventional SC-DAC. In addition, when the SC-DAC of the present invention has a plurality of converting channels, since the reference voltage source is not influenced by the effect of signal dependent loading of any converting channel, so that each converting channel can be regarded to have a separate state, and thus the purpose of channel separation can be achieved.

Abstract: A switched capacitor digital-to-analog converter (SC-DAC) is provided. The SC-DAC of the present invention can eliminate an influence of a reference voltage source caused by a signal dependent loading at each clock cycle, so as to completely solve a harmonic distortion of an analog output signal converted by a conventional SC-DAC. In addition, when the SC-DAC of the present invention has a plurality of converting channels, since the reference voltage source is not influenced by the effect of signal dependent loading of any converting channel, so that each converting channel can be regarded to have a separate state, and thus the purpose of channel separation can be achieved.

Abstract: A flat-cell nonvolatile semiconductor memory. The semiconductor memory includes a plurality of units. Each unit includes word lines, a main bit line, a ground line, sub-bit lines, memory cell columns, and bank-selecting switches. Word lines are disposed in parallel, and the main bit line and the ground line cross the word lines. Sub-bit lines are disposed substantially in parallel to the main bit lines. Each memory cell column includes a plurality of memory cells connected in parallel between respective adjacent two of the sub-bit lines. The bank-selecting switches are used to select one of the memory cell columns. The first one of the bank-selecting switches is disposed between the main bit line and the fourth sub-bit line. The second of the bank-selecting switches is disposed between the main bit line and the second sub-bit line. The third of the bank-selecting switches is disposed between the ground line and the fifth sub-bit line.

Abstract: A double protection virtual ground memory circuit and column decoder. Through the introduction of a double protection circuit, leakage current from the virtual ground memory is reduced and power consumed by the memory circuit is lowered. Ultimately, sensing range of data within the memory by a sense amplifier is improved.