Patents by Inventor Lai Wan CHONG
Lai Wan CHONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11929398Abstract: Present disclosure provides a FinFET structure, including a substrate, a fin protruding from the substrate, including a first portion and a second portion below the first portion, wherein the first portion includes a first dopant concentration of a dopant, and the second portion includes a second dopant concentration of the dopant, the second dopant concentration is greater than the first dopant concentration, a gate over the fin, wherein the second portion of the fin is below a bottom surface of the gate, and an insulating layer over the substrate and proximal to the second portion of the fin, wherein at least a first portion of the insulating layer includes a third dopant concentration of the dopant, the third dopant concentration is greater than the first dopant concentration.Type: GrantFiled: June 1, 2021Date of Patent: March 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun Hsiung Tsai, Lai-Wan Chong, Chien-Wei Lee, Kei-Wei Chen
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Publication number: 20220367635Abstract: Present disclosure provides a FinFET structure, including a substrate, a fin protruding from the substrate, including a first portion and a second portion below the first portion, the second portion includes a lighter-doped region and a heavier-doped region adjacent to the lighter-doped region, wherein the first portion includes a first dopant concentration of a dopant, and the heavier-doped region includes a second dopant concentration of the dopant, the second dopant concentration is greater than the first dopant concentration, a gate over the fin, wherein the second portion of the fin is below a bottom surface of the gate, and an insulating layer over the substrate and proximal to the second portion of the fin, wherein at least a first portion of the insulating layer includes a third dopant concentration of the dopant, the third dopant concentration is greater than the first dopant concentration.Type: ApplicationFiled: July 27, 2022Publication date: November 17, 2022Inventors: CHUN HSIUNG TSAI, LAI-WAN CHONG, CHIEN-WEI LEE, KEI-WEI CHEN
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Patent number: 11450742Abstract: Present disclosure provides a FinFET structure, including a fin and a gate surrounding a first portion of the fin. A dopant concentration in the first portion of the fin is lower than about 1E17/cm3. The FinFET structure further includes an insulating layer surrounding a second portion of the fin. The dopant concentration of the second portion of the fin is greater than about 8E15/cm3. The insulating layer includes a lower layer and an upper layer, and the lower layer is disposed over a substrate connecting to the fin and has a dopant concentration greater than about 1E19/cm3.Type: GrantFiled: October 27, 2017Date of Patent: September 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun Hsiung Tsai, Lai-Wan Chong, Chien-Wei Lee, Kei-Wei Chen
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Publication number: 20210288146Abstract: Present disclosure provides a FinFET structure, including a substrate, a fin protruding from the substrate, including a first portion and a second portion below the first portion, wherein the first portion includes a first dopant concentration of a dopant, and the second portion includes a second dopant concentration of the dopant, the second dopant concentration is greater than the first dopant concentration, a gate over the fin, wherein the second portion of the fin is below a bottom surface of the gate, and an insulating layer over the substrate and proximal to the second portion of the fin, wherein at least a first portion of the insulating layer includes a third dopant concentration of the dopant, the third dopant concentration is greater than the first dopant concentration.Type: ApplicationFiled: June 1, 2021Publication date: September 16, 2021Inventors: CHUN HSIUNG TSAI, LAI-WAN CHONG, CHIEN-WEI LEE, KEI-WEI CHEN
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Patent number: 10153199Abstract: A method of fabricating a semiconductor device. The method includes forming source/drain features in a substrate on opposite sides of a gate structure, forming an etch stop layer over the source/drain features, and depositing a dielectric layer on the etch stop layer. The method further includes performing a first atomic layer etching (ALE) process having a first operating parameter value on the dielectric layer to form a first part of an opening, and performing a second ALE process having a second operating parameter value to extend the opening to expose the source/drain features. The first operating parameter value is different from the second operating parameter value.Type: GrantFiled: May 27, 2016Date of Patent: December 11, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun Hsiung Tsai, Kei-Wei Chen, Lai-Wan Chong, Tsan-Chun Wang
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Publication number: 20180053825Abstract: Present disclosure provides a FinFET structure, including a fin and a gate surrounding a first portion of the fin. A dopant concentration in the first portion of the fin is lower than about 1E17/cm3. The FinFET structure further includes an insulating layer surrounding a second portion of the fin. The dopant concentration of the second portion of the fin is greater than about 8E15/cm3. The insulating layer includes a lower layer and an upper layer, and the lower layer is disposed over a substrate connecting to the fin and has a dopant concentration greater than about 1E19/cm3.Type: ApplicationFiled: October 27, 2017Publication date: February 22, 2018Inventors: CHUN HSIUNG TSAI, LAI-WAN CHONG, CHIEN-WEI LEE, KEI-WEI CHEN
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Patent number: 9806154Abstract: Present disclosure provides a FinFET structure, including a fin and a gate surrounding a first portion of the fin. A dopant concentration in the first portion of the fin is lower than about 1E17/cm3. The FinFET structure further includes an insulating layer surrounding a second portion of the fin. The dopant concentration of the second portion of the fin is greater than about 8E15/cm3. The insulating layer includes a lower layer and an upper layer, and the lower layer is disposed over a substrate connecting to the fin and has a dopant concentration greater than about 1E19/cm3.Type: GrantFiled: January 20, 2015Date of Patent: October 31, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun Hsiung Tsai, Lai-Wan Chong, Chien-Wei Lee, Kei-Wei Chen
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Publication number: 20170278743Abstract: A method of fabricating a semiconductor device. The method includes forming source/drain features in a substrate on opposite sides of a gate structure, forming an etch stop layer over the source/drain features, and depositing a dielectric layer on the etch stop layer. The method further includes performing a first atomic layer etching (ALE) process having a first operating parameter value on the dielectric layer to form a first part of an opening, and performing a second ALE process having a second operating parameter value to extend the opening to expose the source/drain features. The first operating parameter value is different from the second operating parameter value.Type: ApplicationFiled: May 27, 2016Publication date: September 28, 2017Inventors: Chun Hsiung TSAI, Kei-Wei CHEN, Lai-Wan CHONG, Tsan-Chun WANG
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Patent number: 9735271Abstract: A semiconductor device includes an isolation feature in a substrate. The semiconductor device further includes a first source/drain feature in the substrate, wherein a first side of the first source/drain feature contacts the isolation feature, and the first source/drain feature exposes a portion of the isolation feature below a top surface of the substrate. The semiconductor device further includes a silicide layer over the first source/drain feature. The semiconductor device further includes a dielectric layer along the exposed portion of the isolation feature below the top surface of the substrate, wherein the dielectric layer contacts the silicide layer. The semiconductor device further includes a second source/drain feature in the substrate on an opposite side of a gate stack from the first source/drain feature, wherein the second source/drain feature has a substantially uniform thickness.Type: GrantFiled: March 2, 2016Date of Patent: August 15, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen Chu Hsiao, Lai Wan Chong, Chun-Chieh Wang, Ying Min Chou, Hsiang Hsiang Ko, Ying-Lang Wang
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Surface tension modification using silane with hydrophobic functional group for thin film deposition
Patent number: 9698263Abstract: A semiconductor structure that includes crystalline surfaces and amorphous hydrophilic surfaces is provided. The hydrophilic surfaces are treated with silane that includes a hydrophobic functional group, converting the hydrophilic surfaces to hydrophobic surfaces. Chemical vapor deposition or other suitable deposition methods are used to simultaneously deposit a material on both surfaces and due to the surface treatment, the deposited material exhibits superior adherence qualities on both surfaces. In one embodiment, the structure is an opening formed in a semiconductor substrate and bounded by at least one portion of a crystalline silicon surface and at least one portion of an amorphous silicon oxide structure.Type: GrantFiled: November 19, 2015Date of Patent: July 4, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Lai-Wan Chong, Wen-Chu Hsiao, Ying-Min Chou, Hsiang-Hsiang Ko -
Publication number: 20160211326Abstract: Present disclosure provides a FinFET structure, including a fin and a gate surrounding a first portion of the fin. A dopant concentration in the first portion of the fin is lower than about 1E17/cm3. The FinFET structure further includes an insulating layer surrounding a second portion of the fin. The dopant concentration of the second portion of the fin is greater than about 8E15/cm3. The insulating layer includes a lower layer and an upper layer, and the lower layer is disposed over a substrate connecting to the fin and has a dopant concentration greater than about 1E19/cm3.Type: ApplicationFiled: January 20, 2015Publication date: July 21, 2016Inventors: CHUN HSIUNG TSAI, LAI-WAN CHONG, CHIEN-WEI LEE, KEI-WEI CHEN
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SURFACE TENSION MODIFICATION USING SILANE WITH HYDROPHOBIC FUNCTIONAL GROUP FOR THIN FILM DEPOSITION
Publication number: 20160190320Abstract: A semiconductor structure that includes crystalline surfaces and amorphous hydrophilic surfaces is provided. The hydrophilic surfaces are treated with silane that includes a hydrophobic functional group, converting the hydrophilic surfaces to hydrophobic surfaces. Chemical vapor deposition or other suitable deposition methods are used to simultaneously deposit a material on both surfaces and due to the surface treatment, the deposited material exhibits superior adherence qualities on both surfaces. In one embodiment, the structure is an opening formed in a semiconductor substrate and bounded by at least one portion of a crystalline silicon surface and at least one portion of an amorphous silicon oxide structure.Type: ApplicationFiled: November 19, 2015Publication date: June 30, 2016Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Lai-Wan CHONG, Wen-Chu HSIAO, Ying-Min CHOU, Hsiang-Hsiang KO -
Publication number: 20160181427Abstract: A semiconductor device includes an isolation feature in a substrate. The semiconductor device further includes a first source/drain feature in the substrate, wherein a first side of the first source/drain feature contacts the isolation feature, and the first source/drain feature exposes a portion of the isolation feature below a top surface of the substrate. The semiconductor device further includes a silicide layer over the first source/drain feature. The semiconductor device further includes a dielectric layer along the exposed portion of the isolation feature below the top surface of the substrate, wherein the dielectric layer contacts the silicide layer. The semiconductor device further includes a second source/drain feature in the substrate on an opposite side of a gate stack from the first source/drain feature, wherein the second source/drain feature has a substantially uniform thickness.Type: ApplicationFiled: March 2, 2016Publication date: June 23, 2016Inventors: Wen Chu HSIAO, Lai Wan CHONG, Chun-Chieh WANG, Ying Min CHOU, Hsiang Hsiang KO, Ying-Lang WANG
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Patent number: 9324863Abstract: A semiconductor device includes a source/drain feature in a substrate. The source/drain feature has an upper portion and a lower portion, the upper portion having a lower concentration of Ge than the lower portion. A Si-containing layer over the source/drain feature includes a metal silicide layer.Type: GrantFiled: May 2, 2014Date of Patent: April 26, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen Chu Hsiao, Lai Wan Chong, Chun-Chieh Wang, Ying Min Chou, Hsiang Hsiang Ko, Ying-Lang Wang
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Publication number: 20150361547Abstract: A method and an apparatus for forming a cleaning a chemical vapor deposition (CVD) chamber are provided. The method includes providing a chemical vapor deposition (CVD) chamber. The method further includes introducing a remote plasma source into the CVD chamber. The method also includes performing a plasma cleaning process to the CVD chamber by applying a radio-frequency (RF) power in the CVD chamber.Type: ApplicationFiled: June 13, 2014Publication date: December 17, 2015Inventors: Min-Hui LIN, Kuo-Hsien CHENG, Chia-Hsing CHOU, Miao-Cheng LIAO, Lai-Wan CHONG
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Surface tension modification using silane with hydrophobic functional group for thin film deposition
Patent number: 9214393Abstract: A semiconductor structure that includes crystalline surfaces and amorphous hydrophilic surfaces is provided. The hydrophilic surfaces are treated with silane that includes a hydrophobic functional group, converting the hydrophilic surfaces to hydrophobic surfaces. Chemical vapor deposition or other suitable deposition methods are used to simultaneously deposit a material on both surfaces and due to the surface treatment, the deposited material exhibits superior adherence qualities on both surfaces. In one embodiment, the structure is an opening formed in a semiconductor substrate and bounded by at least one portion of a crystalline silicon surface and at least one portion of an amorphous silicon oxide structure.Type: GrantFiled: April 2, 2012Date of Patent: December 15, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Lai Wan Chong, Wen Chu Hsiao, Ying Min Chou, Hsiang Hsiang Ko -
Publication number: 20140239416Abstract: A semiconductor device includes a source/drain feature in a substrate. The source/drain feature has an upper portion and a lower portion, the upper portion having a lower concentration of Ge than the lower portion. A Si-containing layer over the source/drain feature includes a metal silicide layer.Type: ApplicationFiled: May 2, 2014Publication date: August 28, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen Chu HSIAO, Lai Wan CHONG, Chun-Chieh WANG, Ying Min CHOU, Hsiang Hsiang KO, Ying-Lang WANG
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Patent number: 8735255Abstract: In a method of manufacturing a semiconductor device, a source/drain feature is formed over a substrate. A Si-containing layer is formed over the source/drain feature. A metal layer is formed over the Si-containing layer. A metal silicide layer is formed from the metal layer and Si in the Si-containing layer.Type: GrantFiled: May 1, 2012Date of Patent: May 27, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen Chu Hsiao, Lai Wan Chong, Chun-Chieh Wang, Ying Min Chou, Hsiang Hsiang Ko, Ying-Lang Wang
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Publication number: 20130295739Abstract: In a method of manufacturing a semiconductor device, a source/drain feature is formed over a substrate. A Si-containing layer is formed over the source/drain feature. A metal layer is formed over the Si-containing layer. A metal silicide layer is formed from the metal layer and Si in the Si-containing layer.Type: ApplicationFiled: May 1, 2012Publication date: November 7, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen Chu HSIAO, Lai Wan CHONG, Chun-Chieh WANG, Ying Min CHOU, Hsiang Hsiang KO, Ying-Lang WANG
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SURFACE TENSION MODIFICATION USING SILANE WITH HYDROPHOBIC FUNCTIONAL GROUP FOR THIN FILM DEPOSITION
Publication number: 20130256663Abstract: A semiconductor structure that includes crystalline surfaces and amorphous hydrophilic surfaces is provided. The hydrophilic surfaces are treated with silane that includes a hydrophobic functional group, converting the hydrophilic surfaces to hydrophobic surfaces. Chemical vapor deposition or other suitable deposition methods are used to simultaneously deposit a material on both surfaces and due to the surface treatment, the deposited material exhibits superior adherence qualities on both surfaces. In one embodiment, the structure is an opening formed in a semiconductor substrate and bounded by at least one portion of a crystalline silicon surface and at least one portion of an amorphous silicon oxide structure.Type: ApplicationFiled: April 2, 2012Publication date: October 3, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Lai Wan CHONG, Wen Chu HSIAO, Ying Min CHOU, Hsiang Hsiang KO