Abstract: A “weak” undriven state is defined as a signal state, distinguished from conventional unknown and high impedance states, and methods of representing this “weak” undriven state in circuit modelling and power aware digital/mixed-signal simulations for comprehensive and complete RTL-level design verification. The conventional unknown state refers to a circuit element that is powered but has an unknown value, a circuit element that is not powered, or a circuit element having an undriven, floating signal. The unknown state is modified, and the “weak” undriven state refers to a circuit element that is not powered and has an unknown value. The “weak” undriven state can have an electrically high impedance to known supply or ground when no other circuit element is active. The “weak” undriven state distinction is particularly useful to model and verify circuit designs known to be resilient to “weak” undriven states, using event driven logic circuit simulators.

Abstract: A method comprises creating an electronic module design having a plurality of electronic components comprising a plurality of low power enabled components and defining a model of functional behavior and of power behavior. The method also comprises identifying sequential element information correlated with an electronic component based on the models of functional and power behavior. the sequential element information comprising a first control signal and a second control signal. A coverage test is generated based on the sequential element information and is configured to quantify behavior of the electronic component based on a relationship of a plurality of activation states of a first control signal to a plurality of activation states of a second control signal. A simulation file is run to simulate operation of the electronic module design, and a performance status of the electronic module design is determined in response to running the simulation file.

Abstract: A method for boundary port modelling that correctly handles back-to-back isolation intent, level shifter intent and voltage level association, by providing hard association of power domains to soft data objects, such as wires. The method includes identifying a boundary port in a detailed power intent (DPI) for a soft design object (SDO). A non-wire object is inserted in the SDO for the boundary port. In the DPI, a power domain of the boundary port is assigned to the non-wire object.

Abstract: Various embodiments disclosed herein provide for a glitch detection and level detection method that use information contained in the signal itself to determine at which resolution or granularity the glitch detection and level detection operates. In particular, the glitch detection method comprises defining a glitch in terms of a change in the area under the waveform which can serve to disambiguate glitches from noises and other transient side effects of level transmissions. Likewise, the level detection method uses an entropy-based metric to identify levels that are significant in context of the entire signal and not in absolute terms.

Abstract: A method for evaluating tests for fabricated integrated circuit (IC) chips includes providing, design for fault injection (DfFI) instances of an IC design that characterize activatable states of controllable elements in an IC chip based on the IC design. The method also includes fault simulating the IC design a corresponding identified test suite to determine a signature for faults and simulating the IC design with the DfFI instances activated to determine a signature for the DfFI instances. The method includes generating a DfFI-fault equivalence dictionary based on a comparison of the signature of the faults and DfFI instances and generating tests for a fabricated IC chip based on the IC design. The method includes receiving test result data characterizing the tests being applied against the fabricated IC chip with the DfFI instances activated and analyzing the test result data to determine an ability of the tests to detect the faults.

Abstract: A method comprises creating an electronic module design having a plurality of electronic components and defining a model of functional behavior of a subset of the plurality of electronic components, the subset of the plurality of electronic components excluding a first electronic component. Functional behavior of the first electronic component is defined in a user-defined functional design intent file based on a first template, and a power behavior of the first electronic component is defined in a user-defined power design intent file based on a second template. A simulation file is generated based on the model of functional behavior and based on the functional behavior and the power behavior of the first electronic component. The simulation file is run to simulate operation of the electronic module design. A performance status is determined of the electronic module design in response to running the simulation file.

Abstract: A method comprises creating an electronic module design having a plurality of electronic components and defining a model of functional behavior of a subset of the plurality of electronic components, the subset of the plurality of electronic components excluding a first electronic component. Functional behavior of the first electronic component is defined in a user-defined functional design intent file based on a first template, and a power behavior of the first electronic component is defined in a user-defined power design intent file based on a second template. A simulation file is generated based on the model of functional behavior and based on the functional behavior and the power behavior of the first electronic component. The simulation file is run to simulate operation of the electronic module design. A performance status is determined of the electronic module design in response to running the simulation file.

Abstract: A method for boundary port modelling that correctly handles back-to-back isolation intent, level shifter intent and voltage level association, by providing hard association of power domains to soft data objects, such as wires. The method includes identifying a boundary port in a detailed power intent (DPI) for a soft design object (SDO). A non-wire object is inserted in the SDO for the boundary port. In the DPI, a power domain of the boundary port is assigned to the non-wire object.

Abstract: A packaged electronic device has a die with a load circuit, a resistor and an analog to digital converter (ADC). The resistor is coupled between a supply node of the die and a power input of the load circuit. The ADC has a first input coupled to a first terminal of the resistor, and a second input coupled to a second terminal of the resistor to measure a voltage across the resistor while a supply voltage is applied to the supply node to determine a load current conducted by the load circuit. A method of manufacturing a packaged electronic device includes wafer processing to fabricate the load circuit, the resistor and the ADC on or in a die area of the wafer with the resistor coupled between the power input of the load circuit and the supply node of the die area.

Abstract: In one embodiment, a method of operating a computational system to evaluate a device under test, where the device under test is operable to receive a digital code input and output in response a corresponding output. The method injects a plurality of simulated faults into a pre-silicon model of the device under test. For each injected simulated fault, the method inputs a plurality of digital codes to the model. For each input digital code, the method selectively stores the input digital code if a difference, between a corresponding output for the input digital code and a no-fault output for the input, exceeds a predetermined threshold value.

Abstract: A circuit includes circuit portions operating from separate power supplies which are switched sequentially. An output of a first portion powered by a power supply (A) is provided as an input to a second portion powered by another power supply (B). Power supply (A) is switched-ON a delay interval later than power supply (B). In an embodiment, the first portion also receives a control input which enables or disables response of the first portion to changes in its inputs. An active circuit is connected between the control terminal and a constant reference potential node of the circuit, and has one transistor of a current-mirror pair connected across supplies (A) and (B). The active circuit connects the control terminal to the constant reference potential node in the delay interval, but is an open circuit otherwise. Power dissipation in the circuit is thereby reduced.

Abstract: A circuit includes circuit portions operating from separate power supplies which are switched sequentially. An output of a first portion powered by a power supply (A) is provided as an input to a second portion powered by another power supply (B). Power supply (A) is switched-ON a delay interval later than power supply (B). In an embodiment, the first portion also receives a control input which enables or disables response of the first portion to changes in its inputs. An active circuit is connected between the control terminal and a constant reference potential node of the circuit, and has one transistor of a current-mirror pair connected across supplies (A) and (B). The active circuit connects the control terminal to the constant reference potential node in the delay interval, but is an open circuit otherwise. Power dissipation in the circuit is thereby reduced.

Abstract: A circuit includes circuit portions operating from separate power supplies which are switched sequentially. An output of a first portion powered by a power supply (A) is provided as an input to a second portion powered by another power supply (B). Power supply (A) is switched-ON a delay interval later than power supply (B). In an embodiment, the first portion also receives a control input which enables or disables response of the first portion to changes in its inputs. An active circuit is connected between the control terminal and a constant reference potential node of the circuit, and has one transistor of a current-mirror pair connected across supplies (A) and (B). The active circuit connects the control terminal to the constant reference potential node in the delay interval, but is an open circuit otherwise. Power dissipation in the circuit is thereby reduced.

Abstract: A circuit includes circuit portions operating from separate power supplies which are switched sequentially. An output of a first portion powered by a power supply (A) is provided as an input to a second portion powered by another power supply (B). Power supply (A) is switched-ON a delay interval later than power supply (B). In an embodiment, the first portion also receives a control input which enables or disables response of the first portion to changes in its inputs. An active circuit is connected between the control terminal and a constant reference potential node of the circuit, and has one transistor of a current-mirror pair connected across supplies (A) and (B). The active circuit connects the control terminal to the constant reference potential node in the delay interval, but is an open circuit otherwise. Power dissipation in the circuit is thereby reduced.

Abstract: A power management (PM) system architecture for a controlled SoC detects availability of power supply for signal-driving at a given node inside a chip, and uses a timer, a discharge mechanism with trigger for starting/stopping a discharge process, and a comparator for monitoring a measured voltage of an intended node during the discharge process. Enabling the discharge mechanism for a known time period helps detection. Power supply can be internally generated in the chip or from a source on board. The architecture detects if the node is driven or floating, an undriven floating node causing a dip in the measured voltage. The measured voltage does not have a dip when the node is driven. The architecture is also configured so that when there is a required on-board external power supply, an internal power supply is disabled to avoid a race-condition. The architecture obviates a dedicated IO pin for mode-indication.

Abstract: A power management (PM) system architecture for a controlled SoC detects availability of power supply for signal-driving at a given node inside a chip, and uses a timer, a discharge mechanism with trigger for starting/stopping a discharge process, and a comparator for monitoring a measured voltage of an intended node during the discharge process. Enabling the discharge mechanism for a known time period helps detection. Power supply can be internally generated in the chip or from a source on board. The architecture detects if the node is driven or floating, an undriven floating node causing a dip in the measured voltage. The measured voltage does not have a dip when the node is driven. The architecture is also configured so that when there is a required on-board external power supply, an internal power supply is disabled to avoid a race-condition. The architecture obviates a dedicated IO pin for mode-indication.