Patents by Inventor Lakshmi N. Ramanathan
Lakshmi N. Ramanathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160163623Abstract: A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed circuit board. A first flange has a first surface and a second surface. The first surface provides a first one of the terminations, and the second surface is opposite to the first surface. A second flange also has a first surface and a second surface, with the first surface providing a second one of the terminations, and the second surface is opposite to the first surface. A die is mounted to the second surface of the first flange with a material having a melting point in excess of 240° C. An electrical interconnect extends between the die and the second surface of the second flange opposite the termination surface, such that the electrical interconnect, first flange and second flange are substantially housed within a body.Type: ApplicationFiled: February 11, 2016Publication date: June 9, 2016Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Lakshminarayan Viswanathan, Lakshmi N. Ramanathan, Audel A. Sanchez, Fernando A. Santos
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Patent number: 9263375Abstract: A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed circuit board. A first flange has a first surface and a second surface. The first surface provides a first one of the terminations, and the second surface is opposite to the first surface. A second flange also has a first surface and a second surface, with the first surface providing a second one of the terminations, and the second surface is opposite to the first surface. A die is mounted to the second surface of the first flange with a material having a melting point in excess of 240° C. An electrical interconnect extends between the die and the second surface of the second flange opposite the termination surface, such that the electrical interconnect, first flange and second flange are substantially housed within a body.Type: GrantFiled: July 25, 2014Date of Patent: February 16, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Lakshminarayan Viswanathan, Lakshmi N. Ramanathan, Audel A. Sanchez, Fernando A. Santos
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Publication number: 20140332941Abstract: A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed circuit board. A first flange has a first surface and a second surface. The first surface provides a first one of the terminations, and the second surface is opposite to the first surface. A second flange also has a first surface and a second surface, with the first surface providing a second one of the terminations, and the second surface is opposite to the first surface. A die is mounted to the second surface of the first flange with a material having a melting point in excess of 240° C. An electrical interconnect extends between the die and the second surface of the second flange opposite the termination surface, such that the electrical interconnect, first flange and second flange are substantially housed within a body.Type: ApplicationFiled: July 25, 2014Publication date: November 13, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Lakshminarayan Viswanathan, Lakshmi N. Ramanathan, Audel A. Sanchez, Fernando A. Santos
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Patent number: 8803302Abstract: A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed circuit board. A first flange has a first surface and a second surface. The first surface provides a first one of the terminations, and the second surface is opposite to the first surface. A second flange also has a first surface and a second surface, with the first surface providing a second one of the terminations, and the second surface is opposite to the first surface. A die is mounted to the second surface of the first flange with a material having a melting point in excess of 240° C. An electrical interconnect extends between the die and the second surface of the second flange opposite the termination surface, such that the electrical interconnect, first flange and second flange are substantially housed within a body.Type: GrantFiled: May 31, 2012Date of Patent: August 12, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Lakshminarayan Viswanathan, Lakshmi N. Ramanathan, Audel A. Sanchez, Fernando A. Santos
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Publication number: 20130320515Abstract: A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed circuit board. A first flange has a first surface and a second surface. The first surface provides a first one of the terminations, and the second surface is opposite to the first surface. A second flange also has a first surface and a second surface, with the first surface providing a second one of the terminations, and the second surface is opposite to the first surface. A die is mounted to the second surface of the first flange with a material having a melting point in excess of 240° C. An electrical interconnect extends between the die and the second surface of the second flange opposite the termination surface, such that the electrical interconnect, first flange and second flange are substantially housed within a body.Type: ApplicationFiled: May 31, 2012Publication date: December 5, 2013Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Lakshminarayan Viswanathan, Lakshmi N. Ramanathan, Audel A. Sanchez, Fernando A. Santos
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Patent number: 8530346Abstract: An electronic device can include an interconnect level including a bonding pad region. An insulating layer can overlie the interconnect level and include an opening over the bonding pad region. In one embodiment, a conductive stud can lie within the opening and can be substantially encapsulated. In another embodiment, the electronic device can include a barrier layer lying along a side and a bottom of the opening and a conductive stud lying within the opening. The conductive stud can substantially fill the opening. A majority of the conductive stud can lie within the opening. In still another embodiment, a process for forming an electronic device can include forming a conductive stud within the opening wherein from a top view, the conductive stud lies substantially completely within the opening. The process can also include forming a second barrier layer overlying the conductive stud.Type: GrantFiled: October 11, 2010Date of Patent: September 10, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Lakshmi N. Ramanathan, Tien Yu T. Lee, Jinbang Tang
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Patent number: 8236609Abstract: A method (32) of packaging integrated circuit (IC) dies (48) includes applying (36) a laminating material (44) to a wafer (40), and separating (46) the wafer (40) into multiple IC dies (48) such that the laminating material (44) is applied to back surfaces (52) of the IC dies (48). Each of the IC dies (48) is positioned (62) with an active surface (50) facing a support substrate (56). An encapsulant layer (72) is formed (64) overlying the laminating material (44) and the back surfaces (52) of the IC dies (48) from a molding compound (66). The molding compound (66) and the laminating material (44) are removed from the back surfaces (52) of the IC dies (48) to form (76) openings (78) exposing the back surfaces (52). Conductive material (84, 88) is placed in the openings (78) and functions as a heat sink and/or a ground for the IC dies (48).Type: GrantFiled: August 1, 2008Date of Patent: August 7, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Lakshmi N. Ramanathan, Craig S. Amrine, Jianwen Xu
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Patent number: 7950144Abstract: A method is disclosed for controlling warpage in an integrated electronic panel assembly including a plurality of die embedded within an encapsulant. The method comprises determining a number of build-up layers required for the integrated panel assembly. Each build-up layer contributes an amount of concavity to the integrated electronic panel assembly. A level of global convex warpage on the integrated panel assembly is then predicted, wherein the global convex warpage is provided by the presence of an embedded ground plane (EGP) alone within the integrated panel assembly and in the absence of any build-up layers. The embedded ground plane includes openings therein for accepting at least one die within a corresponding opening and it contributes a fixed amount of global convex warpage.Type: GrantFiled: April 30, 2008Date of Patent: May 31, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Lakshmi N. Ramanathan, George R. Leal, Douglas G. Mitchell, Betty H. Yeung
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Publication number: 20110027984Abstract: An electronic device can include an interconnect level including a bonding pad region. An insulating layer can overlie the interconnect level and include an opening over the bonding pad region. In one embodiment, a conductive stud can lie within the opening and can be substantially encapsulated. In another embodiment, the electronic device can include a barrier layer lying along a side and a bottom of the opening and a conductive stud lying within the opening. The conductive stud can substantially fill the opening. A majority of the conductive stud can lie within the opening. In still another embodiment, a process for forming an electronic device can include forming a conductive stud within the opening wherein from a top view, the conductive stud lies substantially completely within the opening. The process can also include forming a second barrier layer overlying the conductive stud.Type: ApplicationFiled: October 11, 2010Publication date: February 3, 2011Applicant: Freescale Semiconductor, Inc.Inventors: Lakshmi N. Ramanathan, Tien Yu T. Lee, Jinbang Tang
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Patent number: 7812448Abstract: An electronic device can include an interconnect level (16) including a bonding pad region (110). An insulating layer (18) can overlie the interconnect level (16) and include an opening (112, 24) over the bonding pad region (110). In one embodiment, a conductive stud (34) can lie within the opening (112, 24) and can be substantially encapsulated. In another embodiment, the electronic device can include a barrier layer (22) lying along a side and a bottom of the opening (112, 24) and a conductive stud (34) lying within the opening (112, 24). The conductive stud (34) can substantially fill the opening (112, 24). A majority of the conductive stud (34) can lie within the opening (112, 24). In still another embodiment, a process for forming an electronic device can include forming a conductive stud (34) within the opening (112, 24) wherein the conductive stud (34) lies substantially completely within the opening (112, 24).Type: GrantFiled: August 7, 2006Date of Patent: October 12, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Lakshmi N. Ramanathan, Tien Yu T. Lee, Jinbang Tang
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Patent number: 7723224Abstract: A method is provided for forming a microelectronic assembly. A contact structure (46) is formed over a first side of a first substrate (20) having a microelectronic device formed over a second side thereof. The contact structure is electrically connected to the microelectronic device. A non-solderable layer (52) is formed over at least a portion of the contact structure and at least a portion of the first substrate. The contact structure and a second substrate (62) are interconnected with solder (68).Type: GrantFiled: June 14, 2006Date of Patent: May 25, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Darrell G. Hill, Philip H. Bowles, Jan Campbell, Terry K. Daly, Jason R. Fender, Lakshmi N. Ramanathan, Neil T. Tracht
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Publication number: 20100029045Abstract: A method (32) of packaging integrated circuit (IC) dies (48) includes applying (36) a laminating material (44) to a wafer (40), and separating (46) the wafer (40) into multiple IC dies (48) such that the laminating material (44) is applied to back surfaces (52) of the IC dies (48). Each of the IC dies (48) is positioned (62) with an active surface (50) facing a support substrate (56). An encapsulant layer (72) is formed (64) overlying the laminating material (44) and the back surfaces (52) of the IC dies (48) from a molding compound (66). The molding compound (66) and the laminating material (44) are removed from the back surfaces (52) of the IC dies (48) to form (76) openings (78) exposing the back surfaces (52). Conductive material (84, 88) is placed in the openings (78) and functions as a heat sink and/or a ground for the IC dies (48).Type: ApplicationFiled: August 1, 2008Publication date: February 4, 2010Applicant: Freescale Semiconductor, Inc.Inventors: Lakshmi N. Ramanathan, Craig S. Amrine, Jianwen Xu
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Publication number: 20090271980Abstract: A method is disclosed for controlling warpage in an integrated electronic panel assembly including a plurality of die embedded within an encapsulant. The method comprises determining a number of build-up layers required for the integrated panel assembly. Each build-up layer contributes an amount of concavity to the integrated electronic panel assembly. A level of global convex warpage on the integrated panel assembly is then predicted, wherein the global convex warpage is provided by the presence of an embedded ground plane (EGP) alone within the integrated panel assembly and in the absence of any build-up layers. The embedded ground plane includes openings therein for accepting at least one die within a corresponding opening and it contributes a fixed amount of global convex warpage.Type: ApplicationFiled: April 30, 2008Publication date: November 5, 2009Inventors: Lakshmi N. Ramanathan, George R. Leal, Douglas G. Mitchell, Betty H. Yeung
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Publication number: 20080029887Abstract: An electronic device can include an interconnect level (16) including a bonding pad region (110). An insulating layer (18) can overlie the interconnect level (16) and include an opening (112, 24) over the bonding pad region (110). In one embodiment, a conductive stud (34) can lie within the opening (112, 24) and can be substantially encapsulated. In another embodiment, the electronic device can include a barrier layer (22) lying along a side and a bottom of the opening (112, 24) and a conductive stud (34) lying within the opening (112, 24). The conductive stud (34) can substantially fill the opening (112, 24). A majority of the conductive stud (34) can lie within the opening (112, 24). In still another embodiment, a process for forming an electronic device can include forming a conductive stud (34) within the opening (112, 24) wherein from a top view, the conductive stud (34) lies substantially completely within the opening (112, 24).Type: ApplicationFiled: August 7, 2006Publication date: February 7, 2008Applicant: Freescale Semiconductor, Inc.Inventors: Lakshmi N. Ramanathan, Tien Yu T. Lee, Jinbang Tang
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Publication number: 20070293033Abstract: A method is provided for forming a microelectronic assembly. A contact structure (46) is formed over a first side of a first substrate (20) having a microelectronic device formed over a second side thereof. The contact structure is electrically connected to the microelectronic device. A non-solderable layer (52) is formed over at least a portion of the contact structure and at least a portion of the first substrate. The contact structure and a second substrate (62) are interconnected with solder (68).Type: ApplicationFiled: June 14, 2006Publication date: December 20, 2007Inventors: Darrell G. Hill, Philip H. Bowles, Jan Campbell, Terry K. Daly, Jason R. Fender, Lakshmi N. Ramanathan, Neil T. Tracht
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Patent number: 6951801Abstract: A process for removing metal from a scribe area of a semiconductor wafer. The metal removed may include exposed metal in a saw path of the scribe area and the metal in a crack stop trench of the scribe area. In one example, copper is removed from the scribe area by wet etching the wafer. In one example, the wet etching process is performed after the removal of an exposed barrier adhesion layer on the wafer surface. Removal of the metal in the saw path may reduce the amount of metal buildup on a saw blade during singulation of the die areas of a wafer.Type: GrantFiled: January 27, 2003Date of Patent: October 4, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Scott K. Pozder, Trent S. Uehling, Lakshmi N. Ramanathan
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Publication number: 20040147097Abstract: A process for removing metal from a scribe area of a semiconductor wafer. The metal removed may include exposed metal in a saw path of the scribe area and the metal in a crack stop trench of the scribe area. In one example, copper is removed from the scribe area by wet etching the wafer. In one example, the wet etching process is performed after the removal of an exposed barrier adhesion layer on the wafer surface. Removal of the metal in the saw path may reduce the amount of metal buildup on a saw blade during singulation of the die areas of a wafer.Type: ApplicationFiled: January 27, 2003Publication date: July 29, 2004Inventors: Scott K. Pozder, Trent S. Uehling, Lakshmi N. Ramanathan