Patents by Inventor Lakshmi N. Reddy
Lakshmi N. Reddy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10496764Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.Type: GrantFiled: May 28, 2019Date of Patent: December 3, 2019Assignee: International Business Machines CorporationInventors: Ying Zhou, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Tellez, Gi-Joon Nam, Jiang Hu
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Publication number: 20190347380Abstract: Techniques that facilitate time-driven placement and/or cloning of components for an integrated circuit are provided. In one example, a system includes an analysis component, a geometric area component and a placement component. The analysis component computes timing information and distance information between a set of transistor components of an integrated circuit. The geometric area component determines at least a first geometric area of the integrated circuit and a second geometric area of the integrated circuit based on the timing information and the distance information. The placement component determines a location for a latch component on the integrated circuit based on an intersection between the first geometric area and the second geometric area.Type: ApplicationFiled: July 24, 2019Publication date: November 14, 2019Inventors: Woohyun Chung, Gi-Joon Nam, Lakshmi N. Reddy
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Patent number: 10417375Abstract: Techniques that facilitate time-driven placement and/or cloning of components for an integrated circuit are provided. In one example, a system includes an analysis component, a geometric area component and a placement component. The analysis component computes timing information and distance information between a set of transistor components of an integrated circuit. The geometric area component determines at least a first geometric area of the integrated circuit and a second geometric area of the integrated circuit based on the timing information and the distance information. The placement component determines a location for a latch component on the integrated circuit based on an intersection between the first geometric area and the second geometric area.Type: GrantFiled: August 29, 2017Date of Patent: September 17, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Woohyun Chung, Gi-Joon Nam, Lakshmi N. Reddy
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Publication number: 20190278873Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.Type: ApplicationFiled: May 28, 2019Publication date: September 12, 2019Inventors: Ying Zhou, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Tellez, Gi-Joon Nam, Jiang Hu
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Publication number: 20190278874Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.Type: ApplicationFiled: May 28, 2019Publication date: September 12, 2019Inventors: Ying Zhou, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Tellez, Gi-Joon Nam, Jiang Hu
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Patent number: 10372837Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.Type: GrantFiled: February 14, 2018Date of Patent: August 6, 2019Assignee: International Business Machines CorporationInventors: Ying Zhou, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Tellez, Gi-Joon Nam, Jiang Hu
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Patent number: 10372836Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.Type: GrantFiled: December 20, 2017Date of Patent: August 6, 2019Assignee: International Business Machines CorporationInventors: Ying Zhou, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Tellez, Gi-Joon Nam, Jiang Hu
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Patent number: 10346558Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.Type: GrantFiled: June 22, 2017Date of Patent: July 9, 2019Assignee: International Business Machines CorporationInventors: Ying Zhou, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Tellez, Gi-Joon Nam, Jiang Hu
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Publication number: 20190188352Abstract: A system and method to perform physical synthesis to transition a logic design to a physical layout of an integrated circuit include obtaining an initial netlist that indicates all components of the integrated circuit including memory elements and edges that interconnect the components. The method also includes generating a graph with at least one of the memory elements and the edges carrying one or more signals to the at least one of the memory elements or from the at least one of the memory elements. The components other than memory elements are not indicated individually on the graph. The netlist is updated based on the graph.Type: ApplicationFiled: December 20, 2017Publication date: June 20, 2019Inventors: Myung-Chul Kim, Arjen Alexander Mets, Gi-Joon Nam, Shyam Ramji, Lakshmi N. Reddy, Alexander J. Suess, Benjamin Trombley, Paul G. Villarrubia
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Publication number: 20190065655Abstract: Techniques that facilitate time-driven placement and/or cloning of components for an integrated circuit are provided. In one example, a system includes an analysis component, a geometric area component and a placement component. The analysis component computes timing information and distance information between a set of transistor components of an integrated circuit. The geometric area component determines at least a first geometric area of the integrated circuit and a second geometric area of the integrated circuit based on the timing information and the distance information. The placement component determines a location for a latch component on the integrated circuit based on an intersection between the first geometric area and the second geometric area.Type: ApplicationFiled: August 29, 2017Publication date: February 28, 2019Inventors: Woohyun Chung, Gi-Joon Nam, Lakshmi N. Reddy
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Publication number: 20190065657Abstract: Techniques that facilitate time-driven placement and/or cloning of components for an integrated circuit are provided. In one example, a system includes an analysis component, a geometric area component and a placement component. The analysis component computes timing information and distance information between a set of transistor components of an integrated circuit. The geometric area component determines at least a first geometric area of the integrated circuit and a second geometric area of the integrated circuit based on the timing information and the distance information. The placement component determines a location for a latch component on the integrated circuit based on an intersection between the first geometric area and the second geometric area.Type: ApplicationFiled: December 14, 2017Publication date: February 28, 2019Inventors: Woohyun Chung, Gi-Joon Nam, Lakshmi N. Reddy
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Publication number: 20180373815Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.Type: ApplicationFiled: February 14, 2018Publication date: December 27, 2018Inventors: Ying Zhou, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Tellez, Gi-Joon Nam, Jiang Hu
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Publication number: 20180373813Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.Type: ApplicationFiled: June 22, 2017Publication date: December 27, 2018Inventors: Ying Zhou, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Tellez, Gi-Joon Nam, Jiang Hu
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Publication number: 20180373814Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.Type: ApplicationFiled: December 20, 2017Publication date: December 27, 2018Inventors: Ying Zhou, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Tellez, Gi-Joon Nam, Jiang Hu
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Publication number: 20180330039Abstract: A computer-implemented method for optimizing microprocessor gates in a microprocessor includes receiving, via a processor, a dataset comprising a model of a plurality of gates of a microprocessor; determining, via the processor, whether a transmission line in the model, if implemented in a physical circuit, would result a signal transmission time less than a predetermined threshold time; applying to the model, via the processor, a proposed gate change to one or more of the plurality of gates; evaluating, via the processor and an area degradation based on the proposed gate change; determining, via the processor, a margin value based on the signal transmission time and an area degradation value; and making, via the processor, a gate change decision based on the margin value.Type: ApplicationFiled: July 11, 2018Publication date: November 15, 2018Inventors: Michael A. Kazda, Arjen A. Mets, Lakshmi N. Reddy, Cindy S. Washburn, Nancy Y. Zhou
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Patent number: 10078722Abstract: A computer-implemented method for optimizing microprocessor gates in a microprocessor includes receiving, via a processor, a dataset comprising a model of a plurality of gates of a microprocessor; determining, via the processor, whether a transmission line in the model, if implemented in a physical circuit, would result a signal transmission time less than a predetermined threshold time; applying to the model, via the processor, a proposed gate change to one or more of the plurality of gates; evaluating, via the processor and an area degradation based on the proposed gate change; determining, via the processor, a margin value based on the signal transmission time and an area degradation value; and making, via the processor, a gate change decision based on the margin value.Type: GrantFiled: June 13, 2016Date of Patent: September 18, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael A. Kazda, Arjen A. Mets, Lakshmi N. Reddy, Cindy S. Washburn, Nancy Y. Zhou
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Publication number: 20170357747Abstract: A computer-implemented method for optimizing microprocessor gates in a microprocessor includes receiving, via a processor, a dataset comprising a model of a plurality of gates of a microprocessor; determining, via the processor, whether a transmission line in the model, if implemented in a physical circuit, would result a signal transmission time less than a predetermined threshold time; applying to the model, via the processor, a proposed gate change to one or more of the plurality of gates; evaluating, via the processor and an area degradation based on the proposed gate change; determining, via the processor, a margin value based on the signal transmission time and an area degradation value; and making, via the processor, a gate change decision based on the margin value.Type: ApplicationFiled: June 13, 2016Publication date: December 14, 2017Inventors: Michael A. Kazda, Arjen A. Mets, Lakshmi N. Reddy, Cindy S. Washburn, Nancy Y. Zhou
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Patent number: 9715565Abstract: A method of performing physical aware technology mapping in a logic synthesis phase of design of an integrated circuit and a system to perform physical aware technology mapping are described. The system includes a memory device to store a logic design of the integrated circuit, and a processor to subdivide a core area representing a sub-block of the integrated circuit into equal-sized grids, the core area including one or more input ports and one or more output ports, to determine a location of each latch in a logic design based on an algorithm, to determine a location of each combinational logic gate in the logic design, and to obtain the technology mapping based on the locations of the one or more latches, the locations of the one or more combinational logic gates, and associated path delays.Type: GrantFiled: June 1, 2016Date of Patent: July 25, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher J. Berry, Pinaki Chakrabarti, Lakshmi N. Reddy, Sourav Saha
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Patent number: 9710585Abstract: A method of performing physical aware technology mapping in a logic synthesis phase of design of an integrated circuit and a system to perform physical aware technology mapping are described. The method includes subdividing a core area representing a sub-block of the integrated circuit into equal-sized grids. The method also includes determining a location of each of one or more latches in the logic design based on an algorithm, determining a location of each of one or more combinational logic gates in the logic design based on the locations of the one or more latches, and obtaining the technology mapping based on the locations of the one or more latches, one or more input ports, or one or more output ports, the locations of the one or more combinational logic gates, and associated path delays.Type: GrantFiled: May 27, 2016Date of Patent: July 18, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher J. Berry, Pinaki Chakrabarti, Lakshmi N. Reddy, Sourav Saha
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Patent number: 9672322Abstract: A system and method of performing physical synthesis of a chip design are described. The method includes performing a baseline physical synthesis to determine a timing slack associated with each device, the timing slack indicating a margin by which timing requirements for the associated device are exceeded, determining that a threshold has been exceeded, the determining based on an analysis of a histogram of the timing slack, and executing a stage-by-stage physical synthesis based on determining that the threshold has been exceeded. The executing the stage-by-stage physical synthesis includes running a stage of the stage-by-stage physical synthesis to determine real timing slack, mapping the real timing slack to virtual timing slack, and running a next stage of the stage-by-stage physical synthesis using the virtual timing slack.Type: GrantFiled: August 27, 2015Date of Patent: June 6, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher J. Berry, Kaustav Guha, Lakshmi N. Reddy, Sourav Saha