Abstract: A semiconductor device having a programmable memory cell which includes a bipolar transistor of which a base region (13) can be provided with a base current through a control transistor (7, 8, 9, 10). The bipolar transistor has an emitter region (12) connected to a first supply line (151) and has a collector region (14) connected to a second supply line (152) through a load (16). A constant potential difference is maintained between the two supply lines (151, 152) during operation. The collector region (14) is laterally electrically insulated and provides a feedback to the control transistor in such a manner that, during operation within a certain voltage domain, a change in the voltage difference between the emitter region (12) and the collector region (14) leads to an opposite change in the conductivity through the control transistor.

Abstract: A charge-coupled device includes a semiconductor body (3) having a semiconductor layer (3) of a first conductivity type adjoining a surface and means for depleting the semiconductor layer throughout its thickness while avoiding breakdown. A sequence (row) of transport electrodes are provided on the surface above the semiconductor layer and are separated by a blocking (isolating) layer from the semiconductor layer and are connected to a clock voltage source to form in the semiconductor layer mutually separated potential wells for storing and transporting information-carrying charge packets. An input stage (I) has a supply zone for supplying majority charge carriers and an input electrode. The input electrode is located between the supply zone and the transport electrodes and is separated by the isolating layer from the semiconductor surface.