Abstract: A method and system of designing an electronic circuit includes dividing a chip area of a design into a plurality of bins, identifying a candidate bin in the plurality of bins, and performing an area reduction on the candidate bin.

Abstract: A process for the automatic handling of requests has a first step of receiving a session request, which results in the issuance of a session token. Upon receipt of a content transfer message accompanied by the previously issued session token, a routing tuple identifying a sender, receiver, and type, the content transfer message also containing content to be transferred, the routing tuple is compared to entries in a process table which resolves into an action and destination. The action and destination associated with the routing tuple and request type are performed if a match is found, or a default action is taken if no match is found, such as placing the content in a user INBOX for future handling. Additionally, the later actions the user takes on the INBOX are examined, and new entries are created in the process table based on the user actions.

Abstract: A method and system of designing an electronic circuit includes dividing a chip area of a design into a plurality of bins, identifying a candidate bin in the plurality of bins, and performing an area reduction on the candidate bin.

Abstract: A method (and system) of applying transforms for modifying a plurality of domains concurrently in a design space, includes creating a sequence of more and less granular placement and netlist modification transforms. A converging design process flow is created by a flexible mechanism in which a select combination of fine-grained transforms are applied to optimize the netlist and placement of a design.

Abstract: An algorithm for efficient restructuring of logic circuitry to improve selected characteristics (delay and/or area). Along a path through the logic circuitry, the logic is converted to equivalent implementations with the same Boolean function using specific choices from the library of available cells, such that these conversions provide an improvement in the cost/benefit for the selected characteristics.

Abstract: A typical domino logic circuit has a foot device, which is the n-type evaluate transistor coupled between the n-type logic circuitry receiving the data inputs and the ground potential. This AND function provides an opportunity to move full domino AND blocks fed by full domino books of any type to the clock input of the source book. This makes the source book act like a pseudo-clocked book with a reset that must propagate from the AND block moved to its clock input. If the AND block were on the critical path, a complete stage of logic can be removed.

Abstract: A redesigning of dynamic logic circuitry inputs into a process implemented in a computer the dynamic logic circuitry to be redesigned as a set of boolean equations. Along a path through the logic circuitry, the logic circuitry is converted into AND and OR books, or blocks of circuitry. Then various portions of these books are compared to a library of AND/OR and OR/AND books. A list of these possible substitutions from the comparison step is produced. From the list, a selection process selects those substitutions providing a best cost benefit.

Abstract: An efficient method for partitioning, for example, FPGA devices is described which optimizes the number of devices required to implement a design. The method involves generating a hierarchical graph of a feasible bipartition of the cells of the design. Feasible pairs are merged, followed by flattening of the hierarchical graph. The number of I/O pins of the new partition is then reduced, upon which a hierarchical graph is derived. A perturbed partition is then generated, followed by restoration of feasibility.

Abstract: An efficient method for partitioning, for example, FPGA devices is described which optimizes the number of devices required to implement a design. The method involves generating a hierarchical graph of a feasible bipartition of the cells of the design. Feasible pairs are merged, followed by flattening of the hierarchical graph. The number of I/O pins of the new partition is then reduced, upon which a hierarchical graph is derived. A perturbed partition is then generated, followed by restoration of feasibility.