Abstract: In calibrating the phase skew between an SDRAM data strobe (“DQS”) signal and data (“DQ”) signal in a device, the data signal driver circuit impedance is adjusted to impair impedance matching on the DQ signal channel while system-level memory tests are performed. The phase skew is stepped through a range during the memory tests, and an error count is determined for each test. The memory tests may emulate mission-mode operation of the device. Following the memory tests, an optimal phase skew corresponding to a lowest error count is determined. The DQS signal may be delayed with respect to the DQ signals by a value corresponding to the optimal phase skew in subsequent mission-mode operation of the device.