Abstract: Embodiments relate to managing layer promotion of interconnects in the routing phase of integrated circuit design. An aspect includes a system to manage layer promotion in a routing phase of integrated circuit design. The system includes a memory device to store instructions, and a processor to execute the instructions to identify a set of candidate interconnects for layer promotion, score and sort the set of candidate interconnects according to a respective score to thereby establish a respective rank, assess routing demand and resource availability based on layer promotion of the set of candidate interconnects, and manage the set of candidate interconnects based on the respective rank and the resource availability, the processor assessing the routing demand and resource availability and managing the set of candidate interconnects iteratively, wherein the processor, in at least one iteration, generates a second set of candidate interconnects by reducing the set of candidate interconnects.

Abstract: A physical synthesis system includes a path straightening module, an ideal critical point identification (ID) module, and a free-space ID module. The path straightening module identifies at least one meandering critical path of a circuit, and generates a reference curve based on dimensions of the critical path. The ideal critical point ID module identifies at least one critical point on the reference curve. The free-space ID module identifies at least one free-space to receive a gate with respect to at least one critical point. The physical synthesis system further includes a free-space selector module and a gate modification module. The free-space selector module determines a modified slack timing value based on relocating the gate to the at least one free-space. The gate modification module moves the gate to the at least one free-space when the modified slack timing value is greater than an initial slack timing value.

Abstract: A physical synthesis system includes a path straightening module, an ideal critical point identification (ID) module, and a free-space ID module. The path straightening module identifies at least one meandering critical path of a circuit, and generates a reference curve based on dimensions of the critical path. The ideal critical point ID module identifies at least one critical point on the reference curve. The free-space ID module identifies at least one free-space to receive a gate with respect to at least one critical point. The physical synthesis system further includes a free-space selector module and a gate modification module. The free-space selector module determines a modified slack timing value based on relocating the gate to the at least one free-space. The gate modification module moves the gate to the at least one free-space when the modified slack timing value is greater than an initial slack timing value.

Abstract: A system and method of performing an intra-run decision during synthesis to determine a physical implementation of a system-on-chip (SoC) logic design are described. The method includes executing a stage of the synthesis with two or more scenarios, each scenario representing a unique combination of values of one or more parameters, and determining a quality measure associated with each of the two or more scenarios. The method also includes performing the intra-run decision by eliminating one or more of the two or more scenarios for execution in a subsequent stage of the synthesis based on the quality measure associated with each of the two or more scenarios.

Abstract: A system and method of performing an intra-run decision during synthesis to determine a physical implementation of a system-on-chip (SoC) logic design are described. The method includes executing a stage of the synthesis with two or more scenarios, each scenario representing a unique combination of values of one or more parameters, and determining a quality measure associated with each of the two or more scenarios. The method also includes performing the intra-run decision by eliminating one or more of the two or more scenarios for execution in a subsequent stage of the synthesis based on the quality measure associated with each of the two or more scenarios.

Abstract: Embodiments relate to managing layer promotion of interconnects in the routing phase of integrated circuit design. An aspect includes a system to manage layer promotion in a routing phase of integrated circuit design. The system includes a memory device to store instructions, and a processor to execute the instructions to identify a set of candidate interconnects for layer promotion, score and sort the set of candidate interconnects according to a respective score to thereby establish a respective rank, assess routing demand and resource availability based on layer promotion of the set of candidate interconnects, and manage the set of candidate interconnects based on the respective rank and the resource availability, the processor assessing the routing demand and resource availability and managing the set of candidate interconnects iteratively, wherein the processor, in at least one iteration, generates a second set of candidate interconnects by reducing the set of candidate interconnects.

Abstract: A system and method of performing an intra-run decision during synthesis to determine a physical implementation of a system-on-chip (SoC) logic design are described. The method includes executing a stage of the synthesis with two or more scenarios, each scenario representing a unique combination of values of one or more parameters, and determining a quality measure associated with each of the two or more scenarios. The method also includes performing the intra-run decision by eliminating one or more of the two or more scenarios for execution in a subsequent stage of the synthesis based on the quality measure associated with each of the two or more scenarios.

Abstract: A system and method of performing an intra-run decision during synthesis to determine a physical implementation of a system-on-chip (SoC) logic design are described. The method includes executing a stage of the synthesis with two or more scenarios, each scenario representing a unique combination of values of one or more parameters, and determining a quality measure associated with each of the two or more scenarios. The method also includes performing the intra-run decision by eliminating one or more of the two or more scenarios for execution in a subsequent stage of the synthesis based on the quality measure associated with each of the two or more scenarios.

Abstract: Embodiments relate to managing layer promotion of interconnects in the routing phase of integrated circuit design. An aspect includes a system to manage layer promotion in a routing phase of integrated circuit design. The system includes a memory device to store instructions, and a processor to execute the instructions to identify a set of candidate interconnects for layer promotion, score and sort the set of candidate interconnects according to a respective score to thereby establish a respective rank, assess routing demand and resource availability based on layer promotion of the set of candidate interconnects, and manage the set of candidate interconnects based on the respective rank and the resource availability, the processor assessing the routing demand and resource availability and managing the set of candidate interconnects iteratively, wherein the processor, in at least one iteration, generates a second set of candidate interconnects by reducing the set of candidate interconnects.

Abstract: Embodiments relate to managing layer promotion of interconnects in the routing phase of integrated circuit design. An aspect includes reducing the set of candidate interconnects for layer promotion based on resource availability. A method of managing includes identifying a set of candidate interconnects for the layer promotion, scoring and sorting the set of candidate interconnects according to a respective score, thereby establishing a respective rank, and assessing routing demand and resource availability based on promoting the set of candidate interconnects. The method also includes managing the set of candidate interconnects based on the respective rank and the assessing, the assessing and the managing being done iteratively and the managing including, in at least one iteration, generating a second set of candidate interconnects based on reducing the set of candidate interconnects.

Abstract: Embodiments relate to managing layer promotion of interconnects in the routing phase of integrated circuit design. An aspect includes reducing the set of candidate interconnects for layer promotion based on resource availability. A method of managing includes identifying a set of candidate interconnects for the layer promotion, scoring and sorting the set of candidate interconnects according to a respective score, thereby establishing a respective rank, and assessing routing demand and resource availability based on promoting the set of candidate interconnects. The method also includes managing the set of candidate interconnects based on the respective rank and the assessing, the assessing and the managing being done iteratively and the managing including, in at least one iteration, generating a second set of candidate interconnects based on reducing the set of candidate interconnects.

Abstract: Embodiments relate to managing layer promotion of interconnects in the routing phase of integrated circuit design. An aspect includes a system to manage layer promotion in a routing phase of integrated circuit design. The system includes a memory device to store instructions, and a processor to execute the instructions to identify a set of candidate interconnects for layer promotion, score and sort the set of candidate interconnects according to a respective score to thereby establish a respective rank, assess routing demand and resource availability based on layer promotion of the set of candidate interconnects, and manage the set of candidate interconnects based on the respective rank and the resource availability, the processor assessing the routing demand and resource availability and managing the set of candidate interconnects iteratively, wherein the processor, in at least one iteration, generates a second set of candidate interconnects by reducing the set of candidate interconnects.

Abstract: A method for performing timing optimization of a detail routed netlist, incorporating statistical variability information, common path pessimism reduction, and capacitative coupling information, in a tightly coupled, incremental manner with minimal perturbations to the placement, routing, and asserted parasitic information. The method corrects violations in a placed and routed design of a VLSI circuit chip, where the design is represented by a netlist describing logical and physical characteristics of the design and by a corresponding timing graph, the method including the steps of: identifying violations in the design; iteratively eliminating the violations by incrementally transforming the logical and the physical characteristics of the design, incorporating in the design only legal placements and routes; and applying incremental timing to evaluate the transformations, and updating the existing timing graphs to reflect changes consisting of the legal placements and routes.

Abstract: A method for performing timing optimization of a detail routed netlist, incorporating statistical variability information, common path pessimism reduction, and capacitative coupling information, in a tightly coupled, incremental manner with minimal perturbations to the placement, routing, and asserted parasitic information. The method corrects violations in a placed and routed design of a VLSI circuit chip, where the design is represented by a netlist describing logical and physical characteristics of the design and by a corresponding timing graph, the method including the steps of: identifying violations in the design; iteratively eliminating the violations by incrementally transforming the logical and the physical characteristics of the design, incorporating in the design only legal placements and routes; and applying incremental timing to evaluate the transformations, and updating the existing timing graphs to reflect changes consisting of the legal placements and routes.

Abstract: A method and system of designing an electronic circuit includes dividing a chip area of a design into a plurality of bins, identifying a candidate bin in the plurality of bins, and performing an area reduction on the candidate bin.