Patents by Inventor Lakshmi Sarath

Lakshmi Sarath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Validation of cache locking using instruction fetch and execution
    Patent number: 9268714
    Abstract: A technique for locking a cache memory device (or portion thereof) which includes the following actions: (i) writing full traversal branching instructions in a cache way of a cache memory device; and (ii) subsequent to the writing step, locking the cache way. The locking action is performed by adjusting cache locking data to indicate that data in the cache way will not be overwritten during normal operations of the cache memory device. The writing action and the locking action are performed by a machine.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: February 23, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Rahul S. Moharil, Lakshmi Sarath
  • Validation of cache locking using instruction fetch and execution
    Patent number: 9164928
    Abstract: A technique for locking a cache memory device (or portion thereof) which includes the following actions: (i) writing full traversal branching instructions in a cache way of a cache memory device; and (ii) subsequent to the writing step, locking the cache way. The locking action is performed by adjusting cache locking data to indicate that data in the cache way will not be overwritten during normal operations of the cache memory device. The writing action and the locking action are performed by a machine.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: October 20, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Rahul S. Moharil, Lakshmi Sarath
  • VALIDATION OF CACHE LOCKING USING INSTRUCTION FETCH AND EXECUTION
    Publication number: 20140351517
    Abstract: A technique for locking a cache memory device (or portion thereof) which includes the following actions: (i) writing full traversal branching instructions in a cache way of a cache memory device; and (ii) subsequent to the writing step, locking the cache way. The locking action is performed by adjusting cache locking data to indicate that data in the cache way will not be overwritten during normal operations of the cache memory device. The writing action and the locking action are performed by a machine.
    Type: Application
    Filed: May 22, 2013
    Publication date: November 27, 2014
    Inventors: Rahul S. Moharil, Lakshmi Sarath
  • VALIDATION OF CACHE LOCKING USING INSTRUCTION FETCH AND EXECUTION
    Publication number: 20140351520
    Abstract: A technique for locking a cache memory device (or portion thereof) which includes the following actions: (i) writing full traversal branching instructions in a cache way of a cache memory device; and (ii) subsequent to the writing step, locking the cache way. The locking action is performed by adjusting cache locking data to indicate that data in the cache way will not be overwritten during normal operations of the cache memory device. The writing action and the locking action are performed by a machine.
    Type: Application
    Filed: January 28, 2014
    Publication date: November 27, 2014
    Applicant: International Business Machines Corporation
    Inventors: Rahul S. Moharil, Lakshmi Sarath